diff mbox series

[4/8] dt-bindings: clock: Add GRF clock definition for RK3528

Message ID 20250301104413.36335-1-ziyao@disroot.org (mailing list archive)
State New
Headers show
Series None | expand

Commit Message

Yao Zi March 1, 2025, 10:44 a.m. UTC
These clocks are for SD/SDIO tuning purpose and come with registers
in GRF syscon.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 include/dt-bindings/clock/rockchip,rk3528-cru.h | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Yao Zi March 1, 2025, 10:53 a.m. UTC | #1
On Sat, Mar 01, 2025 at 10:44:13AM +0000, Yao Zi wrote:
> These clocks are for SD/SDIO tuning purpose and come with registers
> in GRF syscon.

Please ignore this e-mail and refer to the series[1] instead, I missed
--in-reply-to when sending. Sorry for the noise.

Best regards,
Yao Zi

[1]: https://lore.kernel.org/all/20250301104250.36295-1-ziyao@disroot.org/

> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  include/dt-bindings/clock/rockchip,rk3528-cru.h | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h
> index 55a448f5ed6d..0245a53fc334 100644
> --- a/include/dt-bindings/clock/rockchip,rk3528-cru.h
> +++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h
> @@ -414,6 +414,12 @@
>  #define MCLK_I2S2_2CH_SAI_SRC_PRE	402
>  #define MCLK_I2S3_8CH_SAI_SRC_PRE	403
>  #define MCLK_SDPDIF_SRC_PRE		404
> +#define SCLK_SDMMC_DRV			405
> +#define SCLK_SDMMC_SAMPLE		406
> +#define SCLK_SDIO0_DRV			407
> +#define SCLK_SDIO0_SAMPLE		408
> +#define SCLK_SDIO1_DRV			409
> +#define SCLK_SDIO1_SAMPLE		410
>  
>  /* scmi-clocks indices */
>  #define SCMI_PCLK_KEYREADER		0
> -- 
> 2.48.1
>
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h
index 55a448f5ed6d..0245a53fc334 100644
--- a/include/dt-bindings/clock/rockchip,rk3528-cru.h
+++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h
@@ -414,6 +414,12 @@ 
 #define MCLK_I2S2_2CH_SAI_SRC_PRE	402
 #define MCLK_I2S3_8CH_SAI_SRC_PRE	403
 #define MCLK_SDPDIF_SRC_PRE		404
+#define SCLK_SDMMC_DRV			405
+#define SCLK_SDMMC_SAMPLE		406
+#define SCLK_SDIO0_DRV			407
+#define SCLK_SDIO0_SAMPLE		408
+#define SCLK_SDIO1_DRV			409
+#define SCLK_SDIO1_SAMPLE		410
 
 /* scmi-clocks indices */
 #define SCMI_PCLK_KEYREADER		0