From patchwork Tue Mar 4 01:27:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 13999807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3488C282C6 for ; Tue, 4 Mar 2025 01:43:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=YTbM0A4d2BA0UX9kNqCv759I+dQl1/QTsB5TKq4NBgk=; b=C9NfqdEjLjHycBxKUYlofJAApZ uaSHqpvd3tx1YFbpeR5YZL3N27fEp3czHrNFMg9H6aq68kMPId9JAffDmW9M7X7XAR9XJD1aPpPfR s++pfSdUzVFJKmjz7uVwsmjpxc1PplEYNTPttIvgg84IpmLv8QKHgcB4S1E7hJN4MLth1Uha7yopv yCpunharlSmPH3JaOrMRZuHsQreDdrie4NqBxGhOK3fItk+gWZYy2Y6eKT6+d3IVrD3q+ze/hWUvW CYvefAu3C4mTllkNR0CeMTUU070OxcA4YFRokf7q06NjKlWEkGixURn6QNTKu+owTg57K8CvGbWVP 8V3dAO7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpHJ8-00000002nvK-3c9N; Tue, 04 Mar 2025 01:42:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpH7R-00000002m4Q-0PLD for linux-arm-kernel@lists.infradead.org; Tue, 04 Mar 2025 01:30:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 227DDFEC; Mon, 3 Mar 2025 17:31:02 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6208A3F673; Mon, 3 Mar 2025 17:30:46 -0800 (PST) From: Andre Przywara To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Philipp Zabel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 07/15] clk: sunxi-ng: a523: Add support for bus clocks Date: Tue, 4 Mar 2025 01:27:57 +0000 Message-ID: <20250304012805.28594-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250304012805.28594-1-andre.przywara@arm.com> References: <20250304012805.28594-1-andre.przywara@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250303_173049_179568_7E36F558 X-CRM114-Status: GOOD ( 11.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the basic bus clocks for the Allwinner A523 and T527 SoCs. This covers the AHB, APB0 and APB1 clocks. Linux is not supposed to change those clocks, but they are needed as parents for many other mod clocks. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 39 ++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c index 455bca0c344bc..c8a96b642bb1e 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -331,6 +331,39 @@ static CLK_FIXED_FACTOR_HW(pll_npu_2x_clk, "pll-npu-2x", static CLK_FIXED_FACTOR_HW(pll_npu_1x_clk, "pll-npu-1x", &pll_npu_4x_clk.common.hw, 4, 1, 0); + +/************************************************************************** + * bus clocks * + **************************************************************************/ + +static const struct clk_parent_data ahb_apb0_parents[] = { + { .fw_name = "hosc" }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_600M_clk.hw }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb0_parents, 0x510, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); +static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb0_parents, 0x520, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static const struct clk_parent_data apb1_parents[] = { + { .fw_name = "hosc" }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_600M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x524, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + /* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the common @@ -358,6 +391,9 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = { &pll_ve_clk.common, &pll_audio0_4x_clk.common, &pll_npu_4x_clk.common, + &ahb_clk.common, + &apb0_clk.common, + &apb1_clk.common, }; static struct clk_hw_onecell_data sun55i_a523_hw_clks = { @@ -403,6 +439,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = { [CLK_PLL_NPU_4X] = &pll_npu_4x_clk.common.hw, [CLK_PLL_NPU_2X] = &pll_npu_2x_clk.hw, [CLK_PLL_NPU] = &pll_npu_1x_clk.hw, + [CLK_AHB] = &ahb_clk.common.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, }, };