From patchwork Tue Mar 11 12:28:46 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balamanikandan Gunasundar X-Patchwork-Id: 14011783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98EFDC282EC for ; Tue, 11 Mar 2025 12:46:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vZp/PBpTO0CQe1k5qhzlWW1MB8muM/Rry9vIGOGw5hA=; b=A2mCRTUTq1XYjg1lZtmlNKoHOm sZm7QT3PWu2tJx+mztM1lDeOkGsoOkaqkGJzdAnhYFa2apQ65vRuUekD478RkqKwVE6SoN692zIQ9 A3dAuRbmnI0mq2gfAKK3wxe8Ex+oOI8nh1nHG/AGCrCiosHxuJNDpcJI8FtgdEKwUIwYr1ge5D0l+ 1dayh78KBo1Xp9WBsQTma32M/pBz4EyZfPm/+FPwlC5Ro6weWhog+7i8a7Wpak/j7zZM3asqrIIej JRWZip8GOPhWussUxG1TG5Tum8dRy+5b3V03kLslwDxiYkrsDf0EeuIPDlRnqTIuyVEm1bOJAzIFs eXCWg3qg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1trz0O-00000005j4b-0ufe; Tue, 11 Mar 2025 12:46:44 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tryjZ-00000005e7X-44KB; Tue, 11 Mar 2025 12:29:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1741696162; x=1773232162; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wsbYRx34YWCglXy0p0R4CnqDsNR0QSvNibV/OSOSWTc=; b=13BhIx9gbhfHFc+BUjUdIef9dockQIr34QsIsp+uucuQ86Wlbvd4YQvg /2fxTedx+AQkYlCmkSSiTpmjKi7Ef4nysiabikeKC5SoTAQLvXLJylktQ eMfpRGYYVsh4RT7uLkBf55rbpgJPnCXjo8h+D6cXdwJ7L2nSOngZRQstL nhauAMCf8Ru92j33RLp+VKdKuUKV4IiEC11WAyr/f17XeVYD0yVUkETTA HZ9pAm/zisG3N9eJj5xVJozjkXrxRLLZlvhCOP8z2lig5tsnBffVxMoMF exTvJH/ZkEK2Z2ylLAs/xFp9jLRFnD9ZzBsgZbjFktYkz3mBscJRCxS4y Q==; X-CSE-ConnectionGUID: d0aXCjEFQVuCEk822uv6wQ== X-CSE-MsgGUID: 9YqJFWjCSDuq4gNMLOkb/Q== X-IronPort-AV: E=Sophos;i="6.14,239,1736838000"; d="scan'208";a="39234197" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 11 Mar 2025 05:29:19 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Mar 2025 05:29:15 -0700 Received: from che-lt-i64410lx.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 11 Mar 2025 05:29:09 -0700 From: Balamanikandan Gunasundar To: , , , , , , , , , CC: , , , , Subject: [PATCH v2 2/3] dt-bindings: mtd: microchip-nand: add atmel pmecc Date: Tue, 11 Mar 2025 17:58:46 +0530 Message-ID: <20250311122847.90081-3-balamanikandan.gunasundar@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250311122847.90081-1-balamanikandan.gunasundar@microchip.com> References: <20250311122847.90081-1-balamanikandan.gunasundar@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250311_052922_081993_85D80575 X-CRM114-Status: GOOD ( 16.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add bindings for programmable multibit error correction code controller (PMECC). Signed-off-by: Balamanikandan Gunasundar --- Changes in v2: - Rename filename to match compatible string - Add constraints for sam9x7 - Droped unused dt labels .../devicetree/bindings/mtd/atmel-nand.txt | 61 ----------------- .../bindings/mtd/microchip,pmecc.yaml | 67 +++++++++++++++++++ 2 files changed, 67 insertions(+), 61 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt index dbbc17a866f2..1934614a9298 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt @@ -1,64 +1,3 @@ -* ECC engine (PMECC) bindings: - -Required properties: -- compatible: should be one of the following - "atmel,at91sam9g45-pmecc" - "atmel,sama5d4-pmecc" - "atmel,sama5d2-pmecc" - "microchip,sam9x60-pmecc" - "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc" -- reg: should contain 2 register ranges. The first one is pointing to the PMECC - block, and the second one to the PMECC_ERRLOC block. - -Example: - - nfc_io: nfc-io@70000000 { - compatible = "atmel,sama5d3-nfc-io", "syscon"; - reg = <0x70000000 0x8000000>; - }; - - pmecc: ecc-engine@ffffc070 { - compatible = "atmel,at91sam9g45-pmecc"; - reg = <0xffffc070 0x490>, - <0xffffc500 0x100>; - }; - - ebi: ebi@10000000 { - compatible = "atmel,sama5d3-ebi"; - #address-cells = <2>; - #size-cells = <1>; - atmel,smc = <&hsmc>; - reg = <0x10000000 0x10000000 - 0x40000000 0x30000000>; - ranges = <0x0 0x0 0x10000000 0x10000000 - 0x1 0x0 0x40000000 0x10000000 - 0x2 0x0 0x50000000 0x10000000 - 0x3 0x0 0x60000000 0x10000000>; - clocks = <&mck>; - - nand_controller: nand-controller { - compatible = "atmel,sama5d3-nand-controller"; - atmel,nfc-sram = <&nfc_sram>; - atmel,nfc-io = <&nfc_io>; - ecc-engine = <&pmecc>; - #address-cells = <2>; - #size-cells = <1>; - ranges; - - nand@3 { - reg = <0x3 0x0 0x800000>; - atmel,rb = <0>; - - /* - * Put generic NAND/MTD properties and - * subnodes here. - */ - }; - }; - }; - ------------------------------------------------------------------------ - Deprecated bindings (should not be used in new device trees): Required properties: diff --git a/Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml b/Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml new file mode 100644 index 000000000000..98260a691a2e --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/microchip,pmecc.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/microchip,pmecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip pmecc controller + +maintainers: + - Balamanikandan Gunasundar + +description: | + Bindings for microchip Programmable Multibit Error Correction Code + Controller (PMECC). pmecc is a programmable BCH encoder/decoder. This + block is passed as the value to the "ecc-engine" property of microchip + nand flash controller node. + +properties: + compatible: + oneOf: + - enum: + - atmel,at91sam9g45-pmecc + - atmel,sama5d2-pmecc + - atmel,sama5d4-pmecc + - microchip,sam9x60-pmecc + - microchip,sam9x7-pmecc + - items: + - const: microchip,sam9x7-pmecc + - const: atmel,at91sam9g45-pmecc + - items: + - const: microchip,sam9x60-pmecc + - const: atmel,at91sam9g45-pmecc + + reg: + items: + - description: Base address and size of PMECC controller registers + - description: Base address and size of PMECC_ERRLOC controller + + clocks: + description: The clock source for pmecc controller + maxItems: 1 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: microchip,sam9x7-pmecc + then: + properties: + clocks: + description: The clock source for pmecc controller + +unevaluatedProperties: false + +examples: + - | + ecc-engine@ffffc070 { + compatible = "microchip,sam9x7-pmecc"; + reg = <0xffffe000 0x300>, + <0xffffe600 0x100>; + clocks = <&pmc 2 48>; + };