| Message ID | 20250312095411.1392379-2-suraj.gupta2@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for 2500Base-X only configuration | expand |
On Wed, Mar 12, 2025 at 03:24:10PM +0530, Suraj Gupta wrote: > AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. Modify > existing binding description, pcs-handle description and add > 2500base-x in phy-mode for 2500base-X only configuration. > > Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com> > --- > .../devicetree/bindings/net/xlnx,axi-ethernet.yaml | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml > index fb02e579463c..977f55b98f31 100644 > --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml > +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml > @@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem > description: | > Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core > provides connectivity to an external ethernet PHY supporting different > - interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two > + interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two Please re-wrap at 80. > segments of memory for buffering TX and RX, as well as the capability of > offloading TX/RX checksum calculation off the processor. > > + AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed. > + > Management configuration is done through the AXI interface, while payload is > sent and received through means of an AXI DMA controller. This driver > includes the DMA driver code, so this driver is incompatible with AXI DMA > @@ -62,6 +64,7 @@ properties: > - rgmii > - sgmii > - 1000base-x > + - 2500base-x > > xlnx,phy-type: > description: > @@ -118,8 +121,8 @@ properties: > type: object > > pcs-handle: > - description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X > - modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, > + description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/ > + 2500base-x modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, And here. > and "phy-handle" should point to an external PHY if exists. > maxItems: 1 > > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml index fb02e579463c..977f55b98f31 100644 --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml @@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem description: | Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core provides connectivity to an external ethernet PHY supporting different - interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two + interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two segments of memory for buffering TX and RX, as well as the capability of offloading TX/RX checksum calculation off the processor. + AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed. + Management configuration is done through the AXI interface, while payload is sent and received through means of an AXI DMA controller. This driver includes the DMA driver code, so this driver is incompatible with AXI DMA @@ -62,6 +64,7 @@ properties: - rgmii - sgmii - 1000base-x + - 2500base-x xlnx,phy-type: description: @@ -118,8 +121,8 @@ properties: type: object pcs-handle: - description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X - modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, + description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/ + 2500base-x modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists. maxItems: 1
AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. Modify existing binding description, pcs-handle description and add 2500base-x in phy-mode for 2500base-X only configuration. Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com> --- .../devicetree/bindings/net/xlnx,axi-ethernet.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)