From patchwork Tue Mar 18 12:35:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 14020958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DF7DC28B2F for ; Tue, 18 Mar 2025 12:53:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=B4KO5EilifI6yoN+X+vgjDIWDTjv1ZLgvfP6UTByEJs=; b=C8QgDSpsFo27PMQxcMd4tM6a9P DhLWrhJpFHKON4iTCmDXAYlY/qzlDnygtBILoC9/4hnIgtqb7FvbeLlsfIGIB1qgoJkbyF9dY92pn jHL7/IEHaY0qB+I23j6+BlgKZ96Kl9fVWkdw1XzW3qlGhtdi8H2D0+g8eGYCT79LLzAHZ3uYSrBS5 wSIfl3tifl+aQr8Qwl+1uk3qvvHIcV0XllLy5uv5ZMF5JIg8wxRag7k+Ms3JHKvUfEqY8L9nTOw7s +sK+2kT7BlXfo0ILHXCIRKtVpCeLNprREpRQWjhxtUi3wSUTJnRAGD7u5IW/glPMYZKqfpONIrJA4 1QVtfZqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tuWRT-00000005wPX-24QA; Tue, 18 Mar 2025 12:53:11 +0000 Received: from bali.collaboradmins.com ([2a01:4f8:201:9162::2]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tuWBv-00000005th5-2E04; Tue, 18 Mar 2025 12:37:09 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1742301426; bh=RBQJLagYuYN2UxwazhLSW7vvo9/ypKzReOyOidsUhvY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MQLOujXQlvmqwZt7kS43LaYcZp1ocxZA3CyWPZGKggx9GtKndD8/CYOzJfYOICSSs 1IiXIouVK+sknI3YSjZ3rYRTIynRVagFX6/p5mABw/lrfIB4hWhERYCcZoq/ufhy9P 1VU5Nx9uD+xyK/OVY9iXyA8uIX0pumex2Z/dbeMRrSucWBwno2Ydbxybktv4xU/MPk L40SO/HT1BtNpAYJmucXVibqACr1tBh2IXa18FYsx6bYEx+RkCJEgPkRejDX9OZW1n axODbTOOR7mRI1P4XMabSjE+N6JK2S27k446M6WyAZUpHrgDy0Da7cD0CDYmDbrZJ7 xLc5HPq6L0ivQ== Received: from localhost (unknown [84.232.140.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 12FC617E1330; Tue, 18 Mar 2025 13:37:06 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 18 Mar 2025 14:35:42 +0200 Subject: [PATCH v6 08/14] phy: rockchip: samsung-hdptx: Avoid Hz<->hHz unit conversion overhead MIME-Version: 1.0 Message-Id: <20250318-phy-sam-hdptx-bpc-v6-8-8cb1678e7663@collabora.com> References: <20250318-phy-sam-hdptx-bpc-v6-0-8cb1678e7663@collabora.com> In-Reply-To: <20250318-phy-sam-hdptx-bpc-v6-0-8cb1678e7663@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_053707_864305_F5150FDA X-CRM114-Status: GOOD ( 16.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The ropll_tmds_cfg table used to identify the configuration params for the supported rates expects the search key, i.e. bit_rate member of struct ropll_config, to be provided in hHz rather than Hz (1 hHz = 100 Hz). This requires multiple conversions between these units being performed at runtime. Improve implementation clarity and efficiency by consistently using the Hz unit throughout driver's internal data structures and functions. Also rename the rather misleading struct member. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 79 +++++++++++------------ 1 file changed, 39 insertions(+), 40 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 2c0ae2442842fe84a86eba6815125be9d31cc41e..e4f6b1d6d999ae01eb7a9a35ea1748b8a2da339c 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -330,7 +330,7 @@ enum dp_link_rate { }; struct ropll_config { - u32 bit_rate; + unsigned long long rate; u8 pms_mdiv; u8 pms_mdiv_afc; u8 pms_pdiv; @@ -410,45 +410,45 @@ struct rk_hdptx_phy { }; static const struct ropll_config ropll_tmds_cfg[] = { - { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, + { 162000000ULL, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 185625000ULL, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, + { 154000000ULL, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, + { 148500000ULL, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, + { 146250000ULL, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, + { 119000000ULL, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, + { 106500000ULL, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 108000000ULL, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, + { 85500000ULL, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, + { 83500000ULL, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 92812500ULL, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 74250000ULL, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, + { 65000000ULL, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, + { 33750000ULL, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 40000000ULL, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 27000000ULL, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, + { 25175000ULL, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, }; @@ -894,10 +894,10 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); } -static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, +static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate, struct ropll_config *cfg) { - const unsigned int fout = data_rate / 2, fref = 24000; + const unsigned int fout = div_u64(rate, 200), fref = 24000; unsigned long k = 0, lc, k_sub, lc_sub; unsigned int fvco, sdc; u32 mdiv, sdiv, n = 8; @@ -967,14 +967,14 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, } static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) + unsigned long long rate) { const struct ropll_config *cfg = NULL; struct ropll_config rc = {0}; int ret, i; for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (rate == ropll_tmds_cfg[i].bit_rate) { + if (rate == ropll_tmds_cfg[i].rate) { cfg = &ropll_tmds_cfg[i]; break; } @@ -988,8 +988,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, } } - dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n", - cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, + dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n", + __func__, rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); rk_hdptx_pre_power_up(hdptx); @@ -1028,19 +1028,19 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, ret = rk_hdptx_post_enable_pll(hdptx); if (!ret) - hdptx->rate = rate * 100; + hdptx->rate = rate; return ret; } static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) + unsigned long long rate) { rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); - if (rate > HDMI14_MAX_RATE / 100) { + if (rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { @@ -1093,7 +1093,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx) } static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx, - unsigned int rate) + unsigned long long rate) { enum phy_mode mode = phy_get_mode(hdptx->phy); u32 status; @@ -1411,8 +1411,8 @@ static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx) static int rk_hdptx_phy_power_on(struct phy *phy) { struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); - int bus_width = phy_get_bus_width(hdptx->phy); enum phy_mode mode = phy_get_mode(phy); + unsigned long long rate; int ret, lane; /* @@ -1420,10 +1420,10 @@ static int rk_hdptx_phy_power_on(struct phy *phy) * from the HDMI bridge driver until phy_configure_opts_hdmi * becomes available in the PHY API. */ - unsigned int rate = bus_width & 0xfffffff; + rate = phy_get_bus_width(hdptx->phy) & 0xfffffff; + rate *= 100; - dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", - __func__, bus_width, rate); + dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, rate); ret = rk_hdptx_phy_consumer_get(hdptx, rate); if (ret) @@ -1785,7 +1785,7 @@ static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) { struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); - return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100); + return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate); } static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) @@ -1806,18 +1806,17 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - u32 bit_rate = rate / 100; int i; if (rate > HDMI20_MAX_RATE) return rate; for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (bit_rate == ropll_tmds_cfg[i].bit_rate) + if (rate == ropll_tmds_cfg[i].rate) break; if (i == ARRAY_SIZE(ropll_tmds_cfg) && - !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) + !rk_hdptx_phy_clk_pll_calc(rate, NULL)) return -EINVAL; return rate; @@ -1828,7 +1827,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, { struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); - return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); + return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); } static const struct clk_ops hdptx_phy_clk_ops = {