| Message ID | 20250327-kernel-upstreaming-add_gpio_support-v2-1-bbe51f8d66da@blaize.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for Blaize BLZP1600 GPIO driver | expand |
On Thu, Mar 27, 2025 at 11:27:04AM +0000, Nikolaos Pasaloukos wrote: > This is a custom silicon GPIO driver provided by VeriSilicon > Microelectronics. It has 32 input/output ports which can be > configured as edge or level triggered interrupts. It also provides > a de-bounce feature. > This controller is used on the Blaize BLZP1600 SoC. > > Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> > --- > .../bindings/gpio/blaize,blzp1600-gpio.yaml | 77 ++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..8b7842331a22b7b9fbfa42b9c711da99227de2e4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/blaize,blzp1600-gpio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Blaize BLZP1600 GPIO controller > + > +description: > + Blaize BLZP1600 GPIO controller is a design of VeriSilicon APB GPIO v0.2 > + IP block. It has 32 ports each of which are intended to be represented > + as child noeds with the generic GPIO-controller properties as described > + in this binding's file. > + > +maintainers: > + - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> > + - James Cowgill <james.cowgill@blaize.com> > + - Matt Redfearn <matt.redfearn@blaize.com> > + - Neil Jones <neil.jones@blaize.com> > + > +properties: > + $nodename: > + pattern: "^gpio@[0-9a-f]+$" > + > + compatible: > + enum: > + - blaize,blzp1600-gpio > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + ngpios: > + default: 32 > + minimum: 1 > + maximum: 32 > + > + interrupts: > + maxItems: 1 > + > + gpio-line-names: true > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 2 > + > +required: > + - compatible > + - reg > + - gpio-controller > + - '#gpio-cells' > + > +dependencies: > + interrupt-controller: [ interrupts ] > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + gpio: gpio@4c0000 { Label is unused, please drop it if you respin. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > + compatible = "blaize,blzp1600-gpio"; > + reg = <0x004c0000 0x1000>; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + }; > +... > > -- > 2.43.0 >
On 27/03/2025 11:27, Nikolaos Pasaloukos wrote: > This is a custom silicon GPIO driver provided by VeriSilicon > Microelectronics. It has 32 input/output ports which can be > configured as edge or level triggered interrupts. It also provides > a de-bounce feature. > This controller is used on the Blaize BLZP1600 SoC. > > Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> > --- > .../bindings/gpio/blaize,blzp1600-gpio.yaml | 77 ++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..8b7842331a22b7b9fbfa42b9c711da99227de2e4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/blaize,blzp1600-gpio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Blaize BLZP1600 GPIO controller > + > +description: > + Blaize BLZP1600 GPIO controller is a design of VeriSilicon APB GPIO v0.2 > + IP block. It has 32 ports each of which are intended to be represented > + as child noeds with the generic GPIO-controller properties as described Typo here I assume, should be nodes ? Also maybe better worded as: Blaize BLZP1600 GPIO controller is an _implementation_ of the VeriSilicon APB GPIO v0.2 IP block > + in this binding's file. > + > +maintainers: > + - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> > + - James Cowgill <james.cowgill@blaize.com> > + - Matt Redfearn <matt.redfearn@blaize.com> > + - Neil Jones <neil.jones@blaize.com> > + > +properties: > + $nodename: > + pattern: "^gpio@[0-9a-f]+$" > + > + compatible: > + enum: > + - blaize,blzp1600-gpio > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + ngpios: > + default: 32 > + minimum: 1 > + maximum: 32 > + > + interrupts: > + maxItems: 1 > + > + gpio-line-names: true > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 2 > + > +required: > + - compatible > + - reg > + - gpio-controller > + - '#gpio-cells' > + > +dependencies: > + interrupt-controller: [ interrupts ] > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + gpio: gpio@4c0000 { > + compatible = "blaize,blzp1600-gpio"; > + reg = <0x004c0000 0x1000>; > + gpio-controller; > + #gpio-cells = <2>; > + ngpios = <32>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + }; > +... >
diff --git a/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8b7842331a22b7b9fbfa42b9c711da99227de2e4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/blaize,blzp1600-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Blaize BLZP1600 GPIO controller + +description: + Blaize BLZP1600 GPIO controller is a design of VeriSilicon APB GPIO v0.2 + IP block. It has 32 ports each of which are intended to be represented + as child noeds with the generic GPIO-controller properties as described + in this binding's file. + +maintainers: + - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> + - James Cowgill <james.cowgill@blaize.com> + - Matt Redfearn <matt.redfearn@blaize.com> + - Neil Jones <neil.jones@blaize.com> + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + enum: + - blaize,blzp1600-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + ngpios: + default: 32 + minimum: 1 + maximum: 32 + + interrupts: + maxItems: 1 + + gpio-line-names: true + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +dependencies: + interrupt-controller: [ interrupts ] + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpio: gpio@4c0000 { + compatible = "blaize,blzp1600-gpio"; + reg = <0x004c0000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + }; +...
This is a custom silicon GPIO driver provided by VeriSilicon Microelectronics. It has 32 input/output ports which can be configured as edge or level triggered interrupts. It also provides a de-bounce feature. This controller is used on the Blaize BLZP1600 SoC. Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> --- .../bindings/gpio/blaize,blzp1600-gpio.yaml | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+)