| Message ID | 20250328030213.1650990-3-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add some enhancements for i.MX95 PCIe | expand |
On Fri, Mar 28, 2025 at 11:02:09AM +0800, Richard Zhu wrote: > Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 42 +++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 57aa777231ae..6051b3b5928f 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -71,6 +71,9 @@ > #define IMX95_SID_MASK GENMASK(5, 0) > #define IMX95_MAX_LUT 32 > > +#define IMX95_PCIE_RST_CTRL 0x3010 > +#define IMX95_PCIE_COLD_RST BIT(0) > + > #define to_imx_pcie(x) dev_get_drvdata((x)->dev) > > enum imx_pcie_variants { > @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) > return 0; > } > > +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) > +{ > + u32 val; > + > + if (assert) { > + /* > + * From i.MX95 PCIe PHY perspective, the COLD reset toggle > + * should be complete after power-up by the following sequence. > + * > 10us(at power-up) > + * > 10ns(warm reset) > + * |<------------>| > + * ______________ > + * phy_reset ____/ \________________ > + * ____________ > + * ref_clk_en_______________________/ > + * Toggle COLD reset aligned with this sequence for i.MX95 PCIe. > + */ > + regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, > + IMX95_PCIE_COLD_RST); > + /* > + * To make sure delay enough time, do regmap_read_bypassed > + * before udelay(). Since udelay() might not use MMIO, and cause > + * delay time less than setting value. > + */ > + regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, > + &val); > + udelay(15); > + regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, > + IMX95_PCIE_COLD_RST); > + regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, > + &val); > + udelay(10); > + } > + > + return 0; > +} > + > static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) > { > reset_control_assert(imx_pcie->pciephy_reset); > @@ -1762,6 +1802,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .ltssm_mask = IMX95_PCIE_LTSSM_EN, > .mode_off[0] = IMX95_PE0_GEN_CTRL_1, > .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, > + .core_reset = imx95_pcie_core_reset, > .init_phy = imx95_pcie_init_phy, > }, > [IMX8MQ_EP] = { > @@ -1815,6 +1856,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .mode_off[0] = IMX95_PE0_GEN_CTRL_1, > .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, > .init_phy = imx95_pcie_init_phy, > + .core_reset = imx95_pcie_core_reset, > .epc_features = &imx95_pcie_epc_features, > .mode = DW_PCIE_EP_TYPE, > }, > -- > 2.37.1 >
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 57aa777231ae..6051b3b5928f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -71,6 +71,9 @@ #define IMX95_SID_MASK GENMASK(5, 0) #define IMX95_MAX_LUT 32 +#define IMX95_PCIE_RST_CTRL 0x3010 +#define IMX95_PCIE_COLD_RST BIT(0) + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) enum imx_pcie_variants { @@ -773,6 +776,43 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) return 0; } +static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + u32 val; + + if (assert) { + /* + * From i.MX95 PCIe PHY perspective, the COLD reset toggle + * should be complete after power-up by the following sequence. + * > 10us(at power-up) + * > 10ns(warm reset) + * |<------------>| + * ______________ + * phy_reset ____/ \________________ + * ____________ + * ref_clk_en_______________________/ + * Toggle COLD reset aligned with this sequence for i.MX95 PCIe. + */ + regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, + IMX95_PCIE_COLD_RST); + /* + * To make sure delay enough time, do regmap_read_bypassed + * before udelay(). Since udelay() might not use MMIO, and cause + * delay time less than setting value. + */ + regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, + &val); + udelay(15); + regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, + IMX95_PCIE_COLD_RST); + regmap_read_bypassed(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL, + &val); + udelay(10); + } + + return 0; +} + static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { reset_control_assert(imx_pcie->pciephy_reset); @@ -1762,6 +1802,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .ltssm_mask = IMX95_PCIE_LTSSM_EN, .mode_off[0] = IMX95_PE0_GEN_CTRL_1, .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .core_reset = imx95_pcie_core_reset, .init_phy = imx95_pcie_init_phy, }, [IMX8MQ_EP] = { @@ -1815,6 +1856,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IMX95_PE0_GEN_CTRL_1, .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, .init_phy = imx95_pcie_init_phy, + .core_reset = imx95_pcie_core_reset, .epc_features = &imx95_pcie_epc_features, .mode = DW_PCIE_EP_TYPE, },
Add the cold reset toggle for i.MX95 PCIe to align PHY's power up sequency. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 42 +++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)