From patchwork Fri Mar 28 11:14:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 14031858 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECCE2C28B20 for ; Fri, 28 Mar 2025 11:18:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ab6YDwd9m1vECnp5VMXzGhHMMce0Codn+wpuzQzyDpk=; b=tL0rl9I8wmbC8nKE+wGOfqx0wp G4fXfzLVVDdmwgz73CmS8l2/Lv77mdNkbQXlk6P/CMfsEqQCSXQ5yPzcoM5XpaGebRmJsEVQBaWlv 24kfps/hzWeFfJFwEahzo7+3w4DJmtklc3NkpCvtCjFeljb9txUIX+iOIKqc6EIrC0Ts0xKUyyeMb bgbk4nP5HdcOvS05DAg6rRm9C0+VwRuO8Z/vdpfBS/sp6YkY1xhY8Zj0MNzzjQldYvYpcT3O1lLR1 QI+iLgo8S5Mu4nTvtxaBCOEE6ckexM6ZlV2gl0TpBJEwacgzrJGv+B+0RLSbarP/+awSKPVRkX/TG fiBgQ99A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.1 #2 (Red Hat Linux)) id 1ty7jE-0000000DDtD-1U2q; Fri, 28 Mar 2025 11:18:24 +0000 Received: from fllvem-ot04.ext.ti.com ([198.47.19.246]) by bombadil.infradead.org with esmtps (Exim 4.98.1 #2 (Red Hat Linux)) id 1ty7fs-0000000DDQH-1zUt for linux-arm-kernel@lists.infradead.org; Fri, 28 Mar 2025 11:14:57 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 52SBElqm2764921 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 28 Mar 2025 06:14:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1743160487; bh=ab6YDwd9m1vECnp5VMXzGhHMMce0Codn+wpuzQzyDpk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zEPOx7g+jI+FQcCSOjrxWULrLHofgALpzgIMGNkIbYbEkMH8SHn4AF3i8f71jfrrj Lx3rfikDsmcCQNGpEQ8iZkVXk6HHwGs30jMReDKNWUq8W1rZdncNf1bTWNYk4moFFH WcV612VSEVcu60SIRNS5rgaOE2FHVFZrJIiiSkgc= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 52SBElZu013902 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Mar 2025 06:14:47 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 28 Mar 2025 06:14:47 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 28 Mar 2025 06:14:47 -0500 Received: from a0497641-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (a0497641-hp-z2-tower-g9-workstation-desktop-pc.dhcp.ti.com [10.24.69.37] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 52SBEeIq029420; Fri, 28 Mar 2025 06:14:44 -0500 From: Neha Malcom Francis To: , , , , , CC: , , , , Subject: [PATCH v2 1/2] dt-bindings: soc: ti: bist: Add BIST for K3 devices Date: Fri, 28 Mar 2025 16:44:38 +0530 Message-ID: <20250328111439.374748-2-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250328111439.374748-1-n-francis@ti.com> References: <20250328111439.374748-1-n-francis@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250328_041456_602499_BC7B43F1 X-CRM114-Status: GOOD ( 14.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the binding for TI K3 BIST (Built-In Self Test) block. Signed-off-by: Neha Malcom Francis --- .../bindings/soc/ti/ti,j784s4-bist.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/ti,j784s4-bist.yaml diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j784s4-bist.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j784s4-bist.yaml new file mode 100644 index 000000000000..f714a1fc550a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,j784s4-bist.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/ti/ti,j784s4-bist.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 BIST + +maintainers: + - Neha Malcom Francis + +description: + The BIST (Built-In Self Test) module is an IP block present in K3 devices + that support triggering of BIST tests, both PBIST (Memory BIST) and LBIST + (Logic BIST) on a core. Both tests are destructive in nature. At boot, BIST + is executed by hardware for the MCU domain automatically as part of HW POST. + +properties: + compatible: + const: ti,j784s4-bist + + reg: + maxItems: 2 + + reg-names: + items: + - const: cfg + - const: ctrl_mmr + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + ti,bist-under-test: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + the device IDs of the devices under test control of the BIST device, the + number of devices may be more than one. The HW logic will trigger the + tests on all of these devices at once. + +required: + - compatible + - reg + - reg-names + - ti,bist-under-test + +additionalProperties: false + +examples: + - | + #include + bus { + #address-cells = <2>; + #size-cells = <2>; + safety-selftest@33c0000 { + compatible = "ti,j784s4-bist"; + reg = <0x00 0x033c0000 0x00 0x400>, + <0x00 0x0010c1a0 0x00 0x01c>; + reg-names = "cfg", "ctrl_mmr"; + clocks = <&k3_clks 237 7>; + power-domains = <&k3_pds 237 TI_SCI_PD_EXCLUSIVE>; + ti,bist-under-test = <343>, <344>, <365>, <366>; + }; + };