| Message ID | 20250401091713.2765724-3-maz@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: apple: Add support for t6020 | expand |
> From: Marc Zyngier <maz@kernel.org> > Date: Tue, 1 Apr 2025 10:17:02 +0100 > > From: Alyssa Rosenzweig <alyssa@rosenzweig.io> > > t6020 adds some register ranges compared to t8103, so requires > a new compatible as well as the new PHY registers. > > Thanks to Mark and Rob for their helpful suggestions in updating > the binding. Ah, that's how you do it! Thanks Rob. This matches the binding already in use for U-Boot and OpenBSD, so: Reviewed-by: Mark Kettenis <mark.kettenis@xs4all.nl> > Suggested-by: Mark Kettenis <mark.kettenis@xs4all.nl> > Suggested-by: Rob Herring <robh@kernel.org> > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> > Tested-by: Janne Grunau <j@jannau.net> > Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> > [maz: added PHY registers, constraints] > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > .../devicetree/bindings/pci/apple,pcie.yaml | 33 +++++++++++++++---- > 1 file changed, 26 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml > index c8775f9cb0713..c0852be04f6de 100644 > --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml > @@ -17,6 +17,10 @@ description: | > implements its root ports. But the ATU found on most DesignWare > PCIe host bridges is absent. > > + On systems derived from T602x, the PHY registers are in a region > + separate from the port registers. In that case, there is one PHY > + register range per port register range. > + > All root ports share a single ECAM space, but separate GPIOs are > used to take the PCI devices on those ports out of reset. Therefore > the standard "reset-gpios" and "max-link-speed" properties appear on > @@ -30,16 +34,18 @@ description: | > > properties: > compatible: > - items: > - - enum: > - - apple,t8103-pcie > - - apple,t8112-pcie > - - apple,t6000-pcie > - - const: apple,pcie > + oneOf: > + - items: > + - enum: > + - apple,t8103-pcie > + - apple,t8112-pcie > + - apple,t6000-pcie > + - const: apple,pcie > + - const: apple,t6020-pcie > > reg: > minItems: 3 > - maxItems: 6 > + maxItems: 10 > > reg-names: > minItems: 3 > @@ -50,6 +56,10 @@ properties: > - const: port1 > - const: port2 > - const: port3 > + - const: phy0 > + - const: phy1 > + - const: phy2 > + - const: phy3 > > ranges: > minItems: 2 > @@ -98,6 +108,15 @@ allOf: > maxItems: 5 > interrupts: > maxItems: 3 > + - if: > + properties: > + compatible: > + contains: > + const: apple,t6020-pcie > + then: > + properties: > + reg-names: > + minItems: 10 > > examples: > - | > -- > 2.39.2 > > >
diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index c8775f9cb0713..c0852be04f6de 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -17,6 +17,10 @@ description: | implements its root ports. But the ATU found on most DesignWare PCIe host bridges is absent. + On systems derived from T602x, the PHY registers are in a region + separate from the port registers. In that case, there is one PHY + register range per port register range. + All root ports share a single ECAM space, but separate GPIOs are used to take the PCI devices on those ports out of reset. Therefore the standard "reset-gpios" and "max-link-speed" properties appear on @@ -30,16 +34,18 @@ description: | properties: compatible: - items: - - enum: - - apple,t8103-pcie - - apple,t8112-pcie - - apple,t6000-pcie - - const: apple,pcie + oneOf: + - items: + - enum: + - apple,t8103-pcie + - apple,t8112-pcie + - apple,t6000-pcie + - const: apple,pcie + - const: apple,t6020-pcie reg: minItems: 3 - maxItems: 6 + maxItems: 10 reg-names: minItems: 3 @@ -50,6 +56,10 @@ properties: - const: port1 - const: port2 - const: port3 + - const: phy0 + - const: phy1 + - const: phy2 + - const: phy3 ranges: minItems: 2 @@ -98,6 +108,15 @@ allOf: maxItems: 5 interrupts: maxItems: 3 + - if: + properties: + compatible: + contains: + const: apple,t6020-pcie + then: + properties: + reg-names: + minItems: 10 examples: - |