From patchwork Fri Jul 29 16:05:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 1021282 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6TG5I8w008480 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 29 Jul 2011 16:05:39 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QmpYk-0006aJ-NW; Fri, 29 Jul 2011 16:05:11 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QmpYk-0005Rr-84; Fri, 29 Jul 2011 16:05:10 +0000 Received: from mail-fx0-f49.google.com ([209.85.161.49]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QmpYh-0005RX-4I for linux-arm-kernel@lists.infradead.org; Fri, 29 Jul 2011 16:05:07 +0000 Received: by fxd20 with SMTP id 20so3140530fxd.36 for ; Fri, 29 Jul 2011 09:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:user-agent:in-reply-to :references:mime-version:content-transfer-encoding:content-type; bh=OVylJXTUxGFf+BB2T5UuJKGUKYf3plL0//K2yZ/cOLI=; b=I5IKiAiWm5K32SxQYHvsWB/e/owMVxV/hUi17kYdvWMKG3KP404WnCJM+ExtAChzUp WXfkbeHEBViL8JRD5jtfZv2JmvY75qsehJf/cL/4bc2itzKUQfzmwiXoc+PAMk1OKxfj y/UeK08Dj4wl1lDlHimZFRYkXWN3oqw4jxpR4= Received: by 10.223.13.69 with SMTP id b5mr2060111faa.1.1311955505137; Fri, 29 Jul 2011 09:05:05 -0700 (PDT) Received: from flatron.localnet (178-73-0-134.home.aster.pl [178.73.0.134]) by mx.google.com with ESMTPS id c28sm1172693fam.16.2011.07.29.09.05.03 (version=SSLv3 cipher=OTHER); Fri, 29 Jul 2011 09:05:04 -0700 (PDT) From: Tomasz Figa To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/5] ARM: s3c64xx: PM: Mask and acknowledge all UART interrupts during core resume. Date: Fri, 29 Jul 2011 18:05:04 +0200 Message-ID: <2174918.pIpigHPGMA@flatron> User-Agent: KMail/4.7.0 (Linux/3.0.0-gentoo; KDE/4.7.0; x86_64; ; ) In-Reply-To: <5661373.tZL1ZnPyVO@flatron> References: <5661373.tZL1ZnPyVO@flatron> MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110729_120507_435068_4B2DB97C X-CRM114-Status: GOOD ( 16.71 ) X-Spam-Score: -0.8 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.161.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (tomasz.figa[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 T_TO_NO_BRKTS_FREEMAIL To: misformatted and free email service Cc: Kukjin Kim , Ben Dooks X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 29 Jul 2011 16:05:40 +0000 (UTC) From 9fd700af5b0c2289a09736a877f6047d1dcd3268 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 19 Jul 2011 22:21:41 +0200 Subject: [PATCH 1/5] ARM: s3c64xx: PM: Mask and acknowledge all UART interrupts during core resume. On some boards (in my case Tiny6410 from FriendlyARM), after waking up from sleep mode, UART controllers are left in an unclean state with interrupt status bits set. After reenabling interrupts the system starts to get hammered by infinite UART interrupts, which cannot be acknowledged, because of disabled UART bus clock. You can imagine the outcome. This patch deals with the issue by reenabling the bus clock in PCLK mask temporarily, acknowledging and masking all the UART interrupts and then restoring the original PCLK mask value, before interrupts get enabled. Alternatively, the issue could be avoided by moving all the UART interrupt handling to the S3C UART driver and disabling the IRQ on port suspend. Could anyone explain me what is the benefit of having the UART IRQ managed by the generic IRQ infrastructure, while it is used only by a single driver? --- arch/arm/mach-s3c64xx/pm.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index bc1c470..799a212 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c @@ -16,12 +16,14 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -93,12 +95,36 @@ void s3c_pm_configure_extint(void) void s3c_pm_restore_core(void) { + u32 pclkgate, tmp; + int i; + __raw_writel(0, S3C64XX_EINT_MASK); s3c_pm_debug_smdkled(1 << 2, 0); s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); + + tmp = pclkgate = __raw_readl(S3C_PCLK_GATE); + + /* re-start uart clocks */ + tmp |= S3C_CLKCON_PCLK_UART0; + tmp |= S3C_CLKCON_PCLK_UART1; + tmp |= S3C_CLKCON_PCLK_UART2; + tmp |= S3C_CLKCON_PCLK_UART3; + + __raw_writel(tmp, S3C_PCLK_GATE); + + udelay(10); + + for (i = 0; i < 4; ++i) { + __raw_writel(15, S3C_VA_UARTx(i) + S3C64XX_UINTM); + __raw_writel(15, S3C_VA_UARTx(i) + S3C64XX_UINTP); + } + + udelay(10); + + __raw_writel(pclkgate, S3C_PCLK_GATE); } void s3c_pm_save_core(void)