From patchwork Wed Oct 31 19:28:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josh Cartwright X-Patchwork-Id: 1682491 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id D5A6D4005F for ; Wed, 31 Oct 2012 23:17:13 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TThUD-0005AW-OW; Wed, 31 Oct 2012 23:14:14 +0000 Received: from mailserver5.natinst.com ([130.164.80.5] helo=spamkiller05.natinst.com) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TThSi-0004U1-UQ for linux-arm-kernel@lists.infradead.org; Wed, 31 Oct 2012 23:12:45 +0000 Received: from mailserv59-us.natinst.com (nb-hsrp-1338.natinst.com [130.164.19.133]) by spamkiller05.natinst.com (8.14.5/8.14.5) with ESMTP id q9VNCRRM031236; Wed, 31 Oct 2012 18:12:27 -0500 Received: from beefymiracle.amer.corp.natinst.com ([130.164.14.197]) by mailserv59-us.natinst.com (Lotus Domino Release 8.5.3FP2 HF169) with ESMTP id 2012103118122791-846735 ; Wed, 31 Oct 2012 18:12:27 -0500 Received: by beefymiracle.amer.corp.natinst.com (Postfix, from userid 1000) id 28B7C671A6; Wed, 31 Oct 2012 17:12:35 -0600 (CST) Message-Id: <23a299ee5e89cfd17bb9affd8fbb9f41b79cfd46.1351721190.git.josh.cartwright@ni.com> In-Reply-To: References: From: Josh Cartwright Date: Wed, 31 Oct 2012 13:28:49 -0600 Subject: [PATCH 7/8] serial: xilinx_uartps: get clock rate info from dts To: Grant Likely , Rob Herring , Russell King , Mike Turquette , John Stultz , Thomas Gleixner , Alan Cox , Greg Kroah-Hartman , John Linn , Michal Simek X-MIMETrack: Itemize by SMTP Server on MailServ59-US/AUS/H/NIC(Release 8.5.3FP2 HF169|September 14, 2012) at 10/31/2012 06:12:27 PM, Serialize by Router on MailServ59-US/AUS/H/NIC(Release 8.5.3FP2 HF169|September 14, 2012) at 10/31/2012 06:12:28 PM, Serialize complete at 10/31/2012 06:12:28 PM X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.7.7855, 1.0.431, 0.0.0000 definitions=2012-10-31_03:2012-10-31, 2012-10-31, 1970-01-01 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121031_191241_672990_805ECA58 X-CRM114-Status: GOOD ( 16.02 ) X-Spam-Score: 2.7 (++) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_PASS SPF: sender matches SPF record 1.6 DATE_IN_PAST_03_06 Date: is 3 to 6 hours before Received: date -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Michal Simek , devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add support for specifying clock information for the uart clk via the device tree. This eliminates the need to hardcode rates in the device tree. Signed-off-by: Josh Cartwright --- arch/arm/boot/dts/zynq-7000.dtsi | 4 ++-- drivers/tty/serial/xilinx_uartps.c | 30 +++++++++++++++++------------- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index bb3085c..5fb763f 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -44,14 +44,14 @@ compatible = "xlnx,xuartps"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; - clock = <50000000>; + clocks = <&uart_clk 0>; }; uart1: uart@e0001000 { compatible = "xlnx,xuartps"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; - clock = <50000000>; + clocks = <&uart_clk 0>; }; slcr: slcr@f8000000 { diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index 23efe17..adfecbc 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -944,18 +945,20 @@ static int __devinit xuartps_probe(struct platform_device *pdev) int rc; struct uart_port *port; struct resource *res, *res2; - int clk = 0; + struct clk *clk; - const unsigned int *prop; - - prop = of_get_property(pdev->dev.of_node, "clock", NULL); - if (prop) - clk = be32_to_cpup(prop); + clk = of_clk_get(pdev->dev.of_node, 0); if (!clk) { dev_err(&pdev->dev, "no clock specified\n"); return -ENODEV; } + rc = clk_prepare_enable(clk); + if (rc) { + dev_err(&pdev->dev, "could not enable clock\n"); + return -EBUSY; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; @@ -978,7 +981,8 @@ static int __devinit xuartps_probe(struct platform_device *pdev) port->mapbase = res->start; port->irq = res2->start; port->dev = &pdev->dev; - port->uartclk = clk; + port->uartclk = clk_get_rate(clk); + port->private_data = clk; dev_set_drvdata(&pdev->dev, port); rc = uart_add_one_port(&xuartps_uart_driver, port); if (rc) { @@ -1000,14 +1004,14 @@ static int __devinit xuartps_probe(struct platform_device *pdev) static int __devexit xuartps_remove(struct platform_device *pdev) { struct uart_port *port = dev_get_drvdata(&pdev->dev); - int rc = 0; + struct clk *clk = port->private_data; + int rc; /* Remove the xuartps port from the serial core */ - if (port) { - rc = uart_remove_one_port(&xuartps_uart_driver, port); - dev_set_drvdata(&pdev->dev, NULL); - port->mapbase = 0; - } + rc = uart_remove_one_port(&xuartps_uart_driver, port); + dev_set_drvdata(&pdev->dev, NULL); + port->mapbase = 0; + clk_disable_unprepare(clk); return rc; }