From patchwork Fri Apr 4 10:10:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 3937641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9D28D9F1EE for ; Fri, 4 Apr 2014 10:13:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D59BE203E9 for ; Fri, 4 Apr 2014 10:13:13 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CA08D203E3 for ; Fri, 4 Apr 2014 10:13:12 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WW16D-0003tT-JN; Fri, 04 Apr 2014 10:11:49 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WW15y-0004rm-3v; Fri, 04 Apr 2014 10:11:34 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WW15e-0004oH-Eh for linux-arm-kernel@lists.infradead.org; Fri, 04 Apr 2014 10:11:15 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s34AAbNZ008420; Fri, 4 Apr 2014 05:10:37 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s34AAb0c022918; Fri, 4 Apr 2014 05:10:37 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Fri, 4 Apr 2014 05:10:37 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s34AAWpV031341; Fri, 4 Apr 2014 05:10:35 -0500 From: Sekhar Nori To: Tony Lindgren Subject: [PATCH v2 1/3] ARM: OMAP2+: L2 cache: allow different aux ctrl settings Date: Fri, 4 Apr 2014 15:40:27 +0530 Message-ID: <26e5bedd5fa33981e2ef3a8e3e498405bf854765.1396605300.git.nsekhar@ti.com> X-Mailer: git-send-email 1.7.10.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140404_061114_611446_35F6B51E X-CRM114-Status: GOOD ( 11.60 ) X-Spam-Score: -7.5 (-------) Cc: Russell King , Linux OMAP Mailing List , Sekhar Nori , Linux ARM Mailing List X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Different SoCs likely need different L2 cache aux ctrl settings based on use cases and optimizations required. For example, if CMA is always used for coherent memory allocations, there is no need for sharable attribute override bit to be set. Pass aux control settings as argument to the L2 cache initialization function to allow for this. Signed-off-by: Sekhar Nori --- arch/arm/mach-omap2/omap4-common.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 06c6a18..0a2e4f0 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -196,10 +196,8 @@ static void omap4_l2c310_write_sec(unsigned long val, unsigned reg) omap_smc1(smc_op, val); } -static int __init omap_l2_cache_init(void) +static int __init omap_l2_cache_init(u32 aux_ctrl, u32 aux_flags) { - u32 aux_ctrl; - /* * To avoid code running on other OMAPs in * multi-omap builds @@ -212,23 +210,28 @@ static int __init omap_l2_cache_init(void) if (WARN_ON(!l2cache_base)) return -ENOMEM; - /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ - aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR | - L310_AUX_CTRL_NS_LOCKDOWN | - L310_AUX_CTRL_NS_INT_CTRL | - L2C_AUX_CTRL_SHARED_OVERRIDE | - L310_AUX_CTRL_DATA_PREFETCH | - L310_AUX_CTRL_INSTR_PREFETCH; - outer_cache.write_sec = omap4_l2c310_write_sec; if (of_have_populated_dt()) - l2x0_of_init(aux_ctrl, 0xc19fffff); + l2x0_of_init(aux_ctrl, aux_flags); else - l2x0_init(l2cache_base, aux_ctrl, 0xc19fffff); + l2x0_init(l2cache_base, aux_ctrl, aux_flags); return 0; } -omap_early_initcall(omap_l2_cache_init); + +static int __init omap4_l2_cache_init(void) +{ + /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ + u32 aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR | + L310_AUX_CTRL_NS_LOCKDOWN | + L310_AUX_CTRL_NS_INT_CTRL | + L2C_AUX_CTRL_SHARED_OVERRIDE | + L310_AUX_CTRL_DATA_PREFETCH | + L310_AUX_CTRL_INSTR_PREFETCH; + + return omap_l2_cache_init(aux_ctrl, 0xc19fffff); +} +omap_early_initcall(omap4_l2_cache_init); #endif void __iomem *omap4_get_sar_ram_base(void)