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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: okknbTKUQuBKxdTKF5flvpOQODk3mlKr79avucgtD+oEvF5fl58q+V634DO9VYadG/ZWW1eyKf0Cy9W0/1o1Nap++Q6U0g4X6OdjPGncGisr0Y7c2Jv/5bqW29gFUDnqUWZM0ZFA9egB6wYegIOTXZSuBa0AGqIOYbxwxnMIZTNNwBI3rV0NdjiFJb3sOR6wihJ3uaRQ/12RNTvHDTa+biYE3kO0n/8vyJS2v2o1MyVFfcp5J69Z8UEIqMXvA4R9bIp3GPG1FQ0Yub70vxsXomKgsGWjF38PuoNVVdzGYDPd/lSPpSG5fu5lGn5IWFA5cKzW9zJ7ZJWV6aPEJ2gpGJzsb5pZzT8ZjaFeck6SD2rLfTrMj0f/bMJKto2WMoXGuJIlHpioVK0XV2biahckPuKxCHf9TECKRO2mVHLJ1EFfqTgSWm8Ssb/Rq+zeU5yb9ppLDtdG2ayRuMIJaZUdOO13h6wk1wBZQPtdPdbFK6fZRYojKmlx10EdemiGk2K5UTGb134W0b5Bn8RgEraZOMrT0hf3FiKXt+yCdOvygbvIwUi1DA+2naJEdVxmBus13PSoKStmCNAQStUtOM5KKiLmAED8ajnyH+fvkmqKI3J691nvLxPMCX44ZMkxkJdHE5mfMuHWcWuaFThtRVQssy7El9JQfZm9XG44TuX9OCymdDnkhuX25qitBUGN4jpAc6V7i/MefYNwYmPnJgxnMfWu4xpSv5UvXyQlI63nCYdC0F9ga6vDRwLSywi5HtZ+cqHSH8wmWnX3tGCHFejbbHKv4fu+Nnnf3XaPtKKvBLEo3ugX7A8/EnM5kJmpIHG2ZrY5mi8hbv6Yn3W2sziLlIyK658pVlJvwhR2LzrLUgaZB8eATZHVAxl+ASAigtcEvt212uJe2QHUdWR6wJ5WrNKZp1HOdO+qWMGpz8BJJF5Hbei/E6z+g0oLPeEi3DZNMoikYfkue6IsiGS5m8bblJP8i4p8g0JxTZvUr5HP3CFyvCLbMJV88EZ0XVcnoTn4T3qlzdwRIt/TT0gZjZZozr/A6x6KLIatHlJFv4+R/kOtq8ASwpxYnJPBFhX2AgqVJHXxlxU27TTOkhJme48VEzPGdVxy9P46JC/cNjw2DSZcZeKEhhlhJc9IlI+MahTLZqlmOTMDZN2Q5gA5H2MC+MzR9rdcDpfG71+3IqQLOYxR/ApWk8nNjIWIbOKr3Ug2gE30jIkJRKTC7DXcHtAOLGkADacWDH3r/qRAkQCdvsZFdOaud6zZHzF6MuaVkwKVNtJFryPPBhDEkX8ySL7Hn9AdqtAuzvFM20wvf2zVHIsxIOnvr0R3GtQFJi93c5zHfoQzSpr+tcHuulCLY2iZHrIlEEfjXjHQ0s8zCj5LxW56PZ6Pb8ZHyBxIcqOh/+cqSPWhefxDDP3KoI7iAWbNEqw1BG+O0WQ5DLZjoiUfScV25iLFhvvlZvhHOYnAUPFWKKH9x7Tucyu6E+/Ho924O5F/LoLx1UcUEqI1WXJbcoz6eSYmladzfKAS7d2pM9XwaOC4IPXSUyugiNofpA/x4A/0w0OCjw3+cllBCd2ev+BdJPwbhmN+vIPe+q+1OMK3 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8da6173e-ef89-405c-8097-08dbf680c665 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2023 17:28:34.9605 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: COJQFTrbj/HxR9Rg3YyJYbtwqVVPKRIHbZsJuASHKSMwIL3HwtmsS2K/NlkRMn24 X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8360 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231206_092849_949078_E1A40F09 X-CRM114-Status: GOOD ( 17.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SVA cleanup made the SSID logic entirely general so all we need to do is call it with the correct cd table entry for a S1 domain. This is slightly tricky because of the ASID and how the locking works, the simple fix is to just update the ASID once we get the right locks. Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 45 +++++++++++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 7e5721490b7f4c..5a0f0ea30c3f5b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1217,8 +1217,6 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr; - lockdep_assert_held(&master->smmu->asid_lock); - memset(target, 0, sizeof(*target)); target->data[0] = cpu_to_le64( @@ -2685,6 +2683,36 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) return 0; } +static int arm_smmu_s1_set_dev_pasid(struct iommu_domain *domain, + struct device *dev, ioasid_t id) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_device *smmu = master->smmu; + struct arm_smmu_cd target_cd; + int ret = 0; + + mutex_lock(&smmu_domain->init_mutex); + if (!smmu_domain->smmu) + ret = arm_smmu_domain_finalise(smmu_domain, smmu); + else if (smmu_domain->smmu != smmu) + ret = -EINVAL; + mutex_unlock(&smmu_domain->init_mutex); + if (ret) + return ret; + + if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) + return -EINVAL; + + /* + * We can read cd.asid outside the lock because arm_smmu_set_pasid() + * will fix it + */ + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + return arm_smmu_set_pasid(master, to_smmu_domain(domain), id, + &target_cd); +} + static void arm_smmu_update_ste(struct arm_smmu_master *master, struct iommu_domain *sid_domain, bool want_ats) @@ -2713,7 +2741,7 @@ static void arm_smmu_update_ste(struct arm_smmu_master *master, int arm_smmu_set_pasid(struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, - const struct arm_smmu_cd *cd) + struct arm_smmu_cd *cd) { struct iommu_domain *sid_domain = iommu_get_domain_for_dev(master->dev); struct arm_smmu_cd *cdptr; @@ -2737,6 +2765,14 @@ int arm_smmu_set_pasid(struct arm_smmu_master *master, if (ret) goto out_unlock; + /* + * We don't want to obtain to the asid_lock too early, so fix up the + * caller set ASID under the lock in case it changed. + */ + cd->data[0] &= ~cpu_to_le64(CTXDESC_CD_0_ASID); + cd->data[0] |= cpu_to_le64( + FIELD_PREP(CTXDESC_CD_0_ASID, smmu_domain->cd.asid)); + arm_smmu_write_cd_entry(master, pasid, cdptr, cd); arm_smmu_update_ste(master, sid_domain, state.want_ats); @@ -2754,7 +2790,7 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) struct iommu_domain *domain; bool last_ssid = master->cd_table.used_ssids == 1; - domain = iommu_get_domain_for_dev_pasid(dev, pasid, IOMMU_DOMAIN_SVA); + domain = iommu_get_domain_for_dev_pasid(dev, pasid, 0); if (WARN_ON(IS_ERR(domain)) || !domain) return; @@ -3280,6 +3316,7 @@ static struct iommu_ops arm_smmu_ops = { .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = arm_smmu_attach_dev, + .set_dev_pasid = arm_smmu_s1_set_dev_pasid, .map_pages = arm_smmu_map_pages, .unmap_pages = arm_smmu_unmap_pages, .flush_iotlb_all = arm_smmu_flush_iotlb_all, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 19628340ccd632..91b23437f41055 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -786,7 +786,7 @@ void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, int arm_smmu_set_pasid(struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, - const struct arm_smmu_cd *cd); + struct arm_smmu_cd *cd); void arm_smmu_remove_pasid(struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, ioasid_t pasid);