From patchwork Mon Feb 10 10:30:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 3617661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9C81FBF418 for ; Mon, 10 Feb 2014 10:31:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AE8D120155 for ; Mon, 10 Feb 2014 10:31:44 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CBF0220138 for ; Mon, 10 Feb 2014 10:31:42 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCo8v-0005iF-E6; Mon, 10 Feb 2014 10:31:13 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCo8e-0006ox-TX; Mon, 10 Feb 2014 10:30:56 +0000 Received: from mail-ee0-f50.google.com ([74.125.83.50]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCo8c-0006no-AN for linux-arm-kernel@lists.infradead.org; Mon, 10 Feb 2014 10:30:55 +0000 Received: by mail-ee0-f50.google.com with SMTP id d17so2883182eek.9 for ; Mon, 10 Feb 2014 02:30:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :content-type; bh=o/emXMT7PNfWPycbHQyRFYu+SpMcqP4OGjfg3YhjlpU=; b=H8c8DH08ERVL4oqlGT6lTAntkFzkcPdJPFB4RVyLgCg5K84+9L+XA6PymbZKPLlc87 a2P85gbCgvSJwvA862OvaiIsk3h2f3IcZQjie30+kryu8xlQ/zGMEKU1KKi68c4MDY4P ozbwq3GpZAYHR73m5KH2uoVICMgbgFI+5fV0RuuQJfb6dfkKk0VkOlChDpI0xOjCq3e0 lkJAtp9IK3/hY0B/312YJdQwJmuPFDxlf5gB8I2ymS++MrWqyoQhPaEqUUy3Wd4VGoyZ uRB8dk2aBd1y/j1hUzidnOOqv/ob7/8cABJE2INrlO3AsPHgxf1V2bTYYEhsai2GLZtT H+Ww== X-Gm-Message-State: ALoCoQmeZfAPBkwfSC8rb2DachdFyTWLy9DeN9p+hUdbleuhcUnRqfa8wY51BWb5waP+0kYQat4P X-Received: by 10.14.94.3 with SMTP id m3mr2647420eef.54.1392028231817; Mon, 10 Feb 2014 02:30:31 -0800 (PST) Received: from localhost (nat-63.starnet.cz. [178.255.168.63]) by mx.google.com with ESMTPSA id 8sm52902568eeq.15.2014.02.10.02.30.29 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 10 Feb 2014 02:30:30 -0800 (PST) From: Michal Simek To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: zynq: Add support for SOC_BUS Date: Mon, 10 Feb 2014 11:30:22 +0100 Message-Id: <279a88555538534075921b0a8a26ff9b0c49317d.1392028209.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.8.2.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140210_053054_584329_9A9F7C02 X-CRM114-Status: GOOD ( 21.93 ) X-Spam-Score: 1.2 (+) Cc: Mark Rutland , Josh Cartwright , monstr@monstr.eu, Russell King , Pawel Moll , Ian Campbell , Peter Crosthwaite , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Kumar Gala , Steffen Trumtrar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_TVD_MIME_NO_HEADERS, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Provide information through SOC_BUS to user space. Silicon revision is provided through devcfg device. Signed-off-by: Michal Simek --- Based on zynq/cleanup branch --- arch/arm/boot/dts/zynq-7000.dtsi | 5 +++ arch/arm/mach-zynq/Kconfig | 1 + arch/arm/mach-zynq/common.c | 72 +++++++++++++++++++++++++++++++++++++++- arch/arm/mach-zynq/common.h | 1 + arch/arm/mach-zynq/slcr.c | 19 +++++++++++ 5 files changed, 97 insertions(+), 1 deletion(-) -- 1.8.2.3 diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 116f83b5..7284499 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -155,6 +155,11 @@ }; }; + devcfg: devcfg@f8007000 { + compatible = "xlnx,zynq-devcfg-1.00.a"; + reg = <0xf8007000 0x100>; + } ; + global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index f3e6ce4..16ba63f 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -16,5 +16,6 @@ config ARCH_ZYNQ select ARM_GLOBAL_TIMER select MFD_SYSCON select GENERIC_ALLOCATOR + select SOC_BUS help Support for Xilinx Zynq ARM Cortex A9 Platform diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 5755129..9d3c88e 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include #include @@ -36,10 +38,15 @@ #include #include #include +#include #include #include "common.h" +#define ZYNQ_DEVCFG_MCTRL 0x80 +#define ZYNQ_DEVCFG_PS_VERSION_SHIFT 28 +#define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF + void __iomem *zynq_scu_base; static struct platform_device zynq_cpuidle_device = { @@ -47,17 +54,80 @@ static struct platform_device zynq_cpuidle_device = { }; /** + * zynq_get_revision - Get Zynq silicon revision + * + * Return: Silicon version or -1 otherwise + */ +static int __init zynq_get_revision(void) +{ + struct device_node *np; + void __iomem *zynq_devcfg_base; + u32 revision; + + np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.00.a"); + if (!np) { + pr_err("%s: no devcfg node found\n", __func__); + return -1; + } + + zynq_devcfg_base = of_iomap(np, 0); + if (!zynq_devcfg_base) { + pr_err("%s: Unable to map I/O memory\n", __func__); + return -1; + } + + revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL); + revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT; + revision &= ZYNQ_DEVCFG_PS_VERSION_MASK; + + iounmap(zynq_devcfg_base); + + return revision; +} + +/** * zynq_init_machine - System specific initialization, intended to be * called from board specific initialization. */ static void __init zynq_init_machine(void) { + struct soc_device_attribute *soc_dev_attr; + struct soc_device *soc_dev; + struct device *parent = NULL; + /* * 64KB way size, 8-way associativity, parity disabled */ l2x0_of_init(0x02060000, 0xF0F0FFFF); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + goto out; + + system_rev = zynq_get_revision(); + + soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq"); + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev); + soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x", + zynq_slcr_get_device_id()); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->family); + kfree(soc_dev_attr->revision); + kfree(soc_dev_attr->soc_id); + kfree(soc_dev_attr); + goto out; + } + + parent = soc_device_to_device(soc_dev); + +out: + /* + * Finished with the static registrations now; fill in the missing + * devices + */ + of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); platform_device_register(&zynq_cpuidle_device); diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index 953f6a1..26a23fe 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -25,6 +25,7 @@ extern void zynq_slcr_system_reset(void); extern void zynq_slcr_cpu_stop(int cpu); extern void zynq_slcr_cpu_start(int cpu); extern u32 zynq_slcr_get_ocm_config(void); +extern u32 zynq_slcr_get_device_id(void); #ifdef CONFIG_SMP extern void secondary_startup(void); diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index f310081..594b280 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -26,11 +26,14 @@ #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ +#define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */ #define SLCR_OCM_CFG_OFFSET 0x910 /* OCM Address Mapping */ #define SLCR_UNLOCK_MAGIC 0xDF0D #define SLCR_A9_CPU_CLKSTOP 0x10 #define SLCR_A9_CPU_RST 0x1 +#define SLCR_PSS_IDCODE_DEVICE_SHIFT 12 +#define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F static void __iomem *zynq_slcr_base; static struct regmap *zynq_slcr_regmap; @@ -84,6 +87,22 @@ static inline int zynq_slcr_unlock(void) } /** + * zynq_slcr_get_device_id - Read device code id + * + * Return: Device code id + */ +u32 zynq_slcr_get_device_id(void) +{ + u32 val; + + zynq_slcr_read(&val, SLCR_PSS_IDCODE); + val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT; + val &= SLCR_PSS_IDCODE_DEVICE_MASK; + + return val; +} + +/** * zynq_slcr_system_reset - Reset the entire system. */ void zynq_slcr_system_reset(void)