From patchwork Sat Dec 9 21:56:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 13486106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56973C4167B for ; Sat, 9 Dec 2023 21:57:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qymZgPEJhc9LMIwAoXP8uFGI7VdG6vF6wSlqC8gold8=; b=pQi3CFOiHhFGVq x0rHRIRdvp9PB+twI8Uz8eoKzBnasQoi3AUt0GWkhlsfQGsoPyh1jIo+Ms3ySYWqOGPvlkwl+kJUS lZ6qlD4EV03AS9hBfqRDeXpHsmUaCamjSm54AtIuTNdKZ/ewhSjf65dH7FcOjG/l4WFUDrJfvzAYV kb+7xPOHnCtxeiZnfEE/K4nthWqKIqgFDeoB8BcZq0t7+WDmV/W9Q10OLVvGmVkgMBm/fQ2+NUYAa I1cV/eiM9DPGYO945UW+B43SzMZ9vV6AV76KCF/1ytFXvpmzJd0Vt72yWmuRUtMDnz1lzVQvHhD+C aLI0J3FV2X9nNGUD4YEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rC5JO-000aJ9-1Z; Sat, 09 Dec 2023 21:56:38 +0000 Received: from pidgin.makrotopia.org ([185.142.180.65]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rC5JH-000aFk-2I; Sat, 09 Dec 2023 21:56:33 +0000 Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1rC5Iy-0000AX-1S; Sat, 09 Dec 2023 21:56:13 +0000 Date: Sat, 9 Dec 2023 21:56:09 +0000 From: Daniel Golle To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Sabrina Dubroca , Daniel Golle , Jianhui Zhao , Chen-Yu Tsai , "Garmin.Chang" , Sam Shih , Markus Schneider-Pargmann , Alexandre Mergnat , Jiasheng Jiang , Uwe =?iso-8859-1?q?Kleine-K=F6nig?= , Frank Wunderlich , Geert Uytterhoeven , Chanwoo Choi , Dan Carpenter , James Liao , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org Subject: [PATCH v4 3/4] clk: mediatek: Add pcw_chg_shift control Message-ID: <28c8ccd234ba311591b6db0de131fde36d3ec409.1702158423.git.daniel@makrotopia.org> References: <097e82b0d66570763d64be1715517d8b032fcf95.1702158423.git.daniel@makrotopia.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <097e82b0d66570763d64be1715517d8b032fcf95.1702158423.git.daniel@makrotopia.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231209_135631_754413_CEB99B38 X-CRM114-Status: GOOD ( 14.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Sam Shih Introduce pcw_chg_shfit control to replace hardcoded PCW_CHG_MASK macro. This will needed for clocks on the MT7988 SoC. Signed-off-by: Sam Shih Signed-off-by: Daniel Golle --- v4: always set .pcw_chg_shift if .pcw_chg_reg is used instead of having an if-expression in mtk_pll_set_rate_regs(). v3: use git --from ... v2: no changes drivers/clk/mediatek/clk-mt6779.c | 1 + drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 1 + drivers/clk/mediatek/clk-pll.c | 3 +-- drivers/clk/mediatek/clk-pll.h | 2 ++ 8 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index ffedb1fe3c672..e66461f341dd3 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1166,6 +1166,7 @@ static const struct mtk_gate apmixed_clks[] = { .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ .pcw_chg_reg = _pcw_chg_reg, \ + .pcw_chg_shift = PCW_CHG_SHIFT, \ .div_table = _div_table, \ } diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c index 2b261c0e2b61d..184e0cd1dde29 100644 --- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -75,6 +75,7 @@ static const struct mtk_gate apmixed_clks[] = { .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ .pcw_chg_reg = _pcw_chg_reg, \ + .pcw_chg_shift = PCW_CHG_SHIFT, \ .div_table = _div_table, \ } diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c index 41ab4d6896a49..87c5dfa3d1ac4 100644 --- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c @@ -53,6 +53,7 @@ static const struct mtk_gate apmixed_clks[] = { .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ .pcw_chg_reg = _pcw_chg_reg, \ + .pcw_chg_shift = PCW_CHG_SHIFT, \ .en_reg = _en_reg, \ .pll_en_bit = _pll_en_bit, \ } diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c index 3590932acc63a..67bf5ef3f0033 100644 --- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c @@ -56,6 +56,7 @@ static const struct mtk_gate apmixed_clks[] = { .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ .pcw_chg_reg = _pcw_chg_reg, \ + .pcw_chg_shift = PCW_CHG_SHIFT, \ .en_reg = _en_reg, \ .pll_en_bit = _pll_en_bit, \ } diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index 44a4c85a67ef5..ccd6bac7cb1fc 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -54,6 +54,7 @@ static const struct mtk_gate apmixed_clks[] = { .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ .pcw_chg_reg = _pcw_chg_reg, \ + .pcw_chg_shift = PCW_CHG_SHIFT, \ .en_reg = _en_reg, \ .pll_en_bit = _pll_en_bit, \ } diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c index 9b0bc5daeac06..daddca6db44e7 100644 --- a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -39,6 +39,7 @@ .pcw_reg = _pcw_reg, \ .pcw_shift = _pcw_shift, \ .pcw_chg_reg = _pcw_chg_reg, \ + .pcw_chg_shift = PCW_CHG_SHIFT, \ .div_table = _div_table, \ } diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 513ab6b1b3229..139b01ab8d140 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -23,7 +23,6 @@ #define CON0_BASE_EN BIT(0) #define CON0_PWR_ON BIT(0) #define CON0_ISO_EN BIT(1) -#define PCW_CHG_MASK BIT(31) #define AUDPLL_TUNER_EN BIT(31) @@ -114,7 +113,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, pll->data->pcw_shift); val |= pcw << pll->data->pcw_shift; writel(val, pll->pcw_addr); - chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; + chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); writel(chg, pll->pcw_chg_addr); if (pll->tuner_addr) writel(val + 1, pll->tuner_addr); diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index f17278ff15d78..84bd8df13e2e5 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -22,6 +22,7 @@ struct mtk_pll_div_table { #define HAVE_RST_BAR BIT(0) #define PLL_AO BIT(1) #define POSTDIV_MASK GENMASK(2, 0) +#define PCW_CHG_SHIFT 31 struct mtk_pll_data { int id; @@ -48,6 +49,7 @@ struct mtk_pll_data { const char *parent_name; u32 en_reg; u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ + u8 pcw_chg_shift; }; /*