From patchwork Wed Mar 8 09:56:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Murzin X-Patchwork-Id: 9610713 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 38F1760414 for ; Wed, 8 Mar 2017 09:57:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64C6D27CEA for ; Wed, 8 Mar 2017 09:57:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 577C628329; Wed, 8 Mar 2017 09:57:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B5E6B27CEA for ; Wed, 8 Mar 2017 09:57:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Bg6j7fUVlRv1oEOOjSCw2RFZBD/dcsqAIV5GimiG4vU=; b=H+5NvmxA5WsGFb uhXHnWH/9nweB7VwO0Wk7hELTi38VbqLoVkCu/67vXRPQiTkO02keNqv3TnW/LJGEW6j6PVtBmaj0 eRWakvhz5GJbKDhFyUazvRoz1pyrpxA9DLCiL1t2MwsosoDvPVPL2d0RXPREQvdF+FrwQ6hWXahvU XlCYbKmlgYhsxiKrZgnuVhubUoc6pV3P0NWUt5cawp89bZu3ccHtnn6gwmvLJNitGXuKQYr1KtZtN pKWapXEWIxR9RVmklGFGbxdMRzsV301Gz2xON64cIraezz1KLbgkCCJK4sHBrnS31FEaxUwyXg9SI vAf/zkJgshiTUHRo8Nyw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1clYL3-0001P1-Ps; Wed, 08 Mar 2017 09:56:57 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1clYL0-0001Nn-HG for linux-arm-kernel@lists.infradead.org; Wed, 08 Mar 2017 09:56:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62C81C28; Wed, 8 Mar 2017 01:56:33 -0800 (PST) Received: from [10.1.78.64] (unknown [10.1.78.64]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 934333F23B; Wed, 8 Mar 2017 01:56:32 -0800 (PST) Subject: Re: [PATCH v2 2/4] ARM: nommu: dynamic exception base address setting To: Greg Ungerer , afzal.mohd.ma@gmail.com References: <314159a7-b664-1256-647d-c05880ad7710@uclinux.org> From: Vladimir Murzin Message-ID: <29b174a1-bd4f-b030-23b7-ff6a7b4c9e83@arm.com> Date: Wed, 8 Mar 2017 09:56:23 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <314159a7-b664-1256-647d-c05880ad7710@uclinux.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170308_015654_603543_5F8AC47B X-CRM114-Status: GOOD ( 20.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux@armlinux.org.uk, "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On 08/03/17 03:21, Greg Ungerer wrote: > > Hi Afzal, > > On 21/01/17 19:20, afzal mohammed write: >> No-MMU dynamic exception base address configuration on CP15 >> processors. In the case of low vectors, decision based on whether >> security extensions are enabled & whether remap vectors to RAM >> CONFIG option is selected. >> >> For no-MMU without CP15, current default value of 0x0 is retained. >> >> Signed-off-by: afzal mohammed > > This patch (which is in mainline now as commit f8300a0b5d) breaks > my patch series to support running the Versatile QEMU target with > a nommu configured linux kernel. This series can be found here: > > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-February/490653.html > > The problem is that QEMU is failing out with: > > qemu: fatal: Trying to execute code outside RAM or ROM at 0x41069264 > > when this your patch is applied. > > >> diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c >> index 2740967727e2..20ac52579952 100644 >> --- a/arch/arm/mm/nommu.c >> +++ b/arch/arm/mm/nommu.c >> @@ -11,6 +11,7 @@ >> #include >> >> #include >> +#include >> #include >> #include >> #include >> @@ -22,6 +23,8 @@ >> >> #include "mm.h" >> >> +unsigned long vectors_base; >> + >> #ifdef CONFIG_ARM_MPU >> struct mpu_rgn_info mpu_rgn_info; >> >> @@ -278,15 +281,60 @@ static void sanity_check_meminfo_mpu(void) {} >> static void __init mpu_setup(void) {} >> #endif /* CONFIG_ARM_MPU */ >> >> +#ifdef CONFIG_CPU_CP15 >> +#ifdef CONFIG_CPU_HIGH_VECTOR >> +static unsigned long __init setup_vectors_base(void) >> +{ >> + unsigned long reg = get_cr(); >> + >> + set_cr(reg | CR_V); >> + return 0xffff0000; >> +} >> +#else /* CONFIG_CPU_HIGH_VECTOR */ >> +/* Write exception base address to VBAR */ >> +static inline void set_vbar(unsigned long val) >> +{ >> + asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); >> +} >> + >> +/* >> + * Security extensions, bits[7:4], permitted values, >> + * 0b0000 - not implemented, 0b0001/0b0010 - implemented >> + */ >> +static inline bool security_extensions_enabled(void) >> +{ >> + return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4); > > The problem is here. This ends up generating the asm code: > > 2ebacc: ee103f31 mrc 15, 0, r3, cr0, cr1, {1} > > QEMU loses it on running this (confirmed by single stepping here). > > Is this valid for an ARM926EJ? > Or is it QEMU that is at fault here... > > I can see that this would be valid for an ARM11 for example > (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/CHDGIJFB.html) > > But I could not see that it is valid on an ARM926 > (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0198e/I1003211.html) > > Maybe I am looking in the wrong place though. > > Thoughts? I'm wondering if something like bellow would help? Cheers Vladimir > > Regards > Greg > > diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 3b5c7aa..25542ec 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -303,7 +303,11 @@ static inline void set_vbar(unsigned long val) */ static inline bool security_extensions_enabled(void) { +#if __LINUX_ARM_ARCH__ < 6 + return 0; +#else return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4); +#endif } static unsigned long __init setup_vectors_base(void)