Message ID | 3-v1-1b720dce51d1+4f44-smmuv3_tidy_jgg@nvidia.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Tidy some minor things in the stream table/cd table area | expand |
Hi Jason, On Mon, Jun 03, 2024 at 07:31:29PM -0300, Jason Gunthorpe wrote: > The top of the 2 level stream table is (at most) 128k entries big, and two > high order allocations are required. One of __le64 which is programmed > into the HW (1M), and one of struct arm_smmu_strtab_l1_desc which holds > the CPU pointer (3M). > > There is no reason to store the l2ptr_dma as nothing reads it. devm stores > a copy of it and the DMA memory will be freed via devm mechanisms. span is > a constant of 8+1. Remove both. > This caught my eye before, I imagine(although I was not there) there was some thought about having different spans per SMMUs maybe, but that’s not the case. > This removes 16 bytes from each arm_smmu_l1_ctx_desc and saves up to 2M of > memory per iommu instance. > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Mostafa Saleh <smostafa@google.com> > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 +++++++------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 --- > 2 files changed, 7 insertions(+), 10 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index d27dd0600bf1df..735dd9ff61890e 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1448,12 +1448,12 @@ bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd) > > /* Stream table manipulation functions */ > static void > -arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc) > +arm_smmu_write_strtab_l1_desc(__le64 *dst, dma_addr_t l2ptr_dma, u8 span) > { > u64 val = 0; > > - val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span); > - val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK; > + val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, span); > + val |= l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK; > > /* The HW has 64 bit atomicity with stores to the L2 STE table */ > WRITE_ONCE(*dst, cpu_to_le64(val)); > @@ -1655,6 +1655,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) > { > size_t size; > void *strtab; > + dma_addr_t l2ptr_dma; > struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; > struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[sid >> STRTAB_SPLIT]; > > @@ -1664,9 +1665,8 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) > size = (1 << STRTAB_SPLIT) * sizeof(struct arm_smmu_ste); > strtab = &cfg->strtab.l1_desc[sid >> STRTAB_SPLIT]; > > - desc->span = STRTAB_SPLIT + 1; > - desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma, > - GFP_KERNEL); > + desc->l2ptr = > + dmam_alloc_coherent(smmu->dev, size, &l2ptr_dma, GFP_KERNEL); > if (!desc->l2ptr) { > dev_err(smmu->dev, > "failed to allocate l2 stream table for SID %u\n", > @@ -1675,7 +1675,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) > } > > arm_smmu_init_initial_stes(desc->l2ptr, 1 << STRTAB_SPLIT); > - arm_smmu_write_strtab_l1_desc(strtab, desc); > + arm_smmu_write_strtab_l1_desc(strtab, l2ptr_dma, STRTAB_SPLIT + 1); > return 0; > } > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 4769780259affc..280a04bfb7230c 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -577,10 +577,7 @@ struct arm_smmu_priq { > > /* High-level stream table and context descriptor structures */ > struct arm_smmu_strtab_l1_desc { > - u8 span; > - > struct arm_smmu_ste *l2ptr; > - dma_addr_t l2ptr_dma; > }; > > struct arm_smmu_ctx_desc { > -- > 2.45.2 >
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d27dd0600bf1df..735dd9ff61890e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1448,12 +1448,12 @@ bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd) /* Stream table manipulation functions */ static void -arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc) +arm_smmu_write_strtab_l1_desc(__le64 *dst, dma_addr_t l2ptr_dma, u8 span) { u64 val = 0; - val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span); - val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK; + val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, span); + val |= l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK; /* The HW has 64 bit atomicity with stores to the L2 STE table */ WRITE_ONCE(*dst, cpu_to_le64(val)); @@ -1655,6 +1655,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) { size_t size; void *strtab; + dma_addr_t l2ptr_dma; struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[sid >> STRTAB_SPLIT]; @@ -1664,9 +1665,8 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) size = (1 << STRTAB_SPLIT) * sizeof(struct arm_smmu_ste); strtab = &cfg->strtab.l1_desc[sid >> STRTAB_SPLIT]; - desc->span = STRTAB_SPLIT + 1; - desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma, - GFP_KERNEL); + desc->l2ptr = + dmam_alloc_coherent(smmu->dev, size, &l2ptr_dma, GFP_KERNEL); if (!desc->l2ptr) { dev_err(smmu->dev, "failed to allocate l2 stream table for SID %u\n", @@ -1675,7 +1675,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) } arm_smmu_init_initial_stes(desc->l2ptr, 1 << STRTAB_SPLIT); - arm_smmu_write_strtab_l1_desc(strtab, desc); + arm_smmu_write_strtab_l1_desc(strtab, l2ptr_dma, STRTAB_SPLIT + 1); return 0; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 4769780259affc..280a04bfb7230c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -577,10 +577,7 @@ struct arm_smmu_priq { /* High-level stream table and context descriptor structures */ struct arm_smmu_strtab_l1_desc { - u8 span; - struct arm_smmu_ste *l2ptr; - dma_addr_t l2ptr_dma; }; struct arm_smmu_ctx_desc {
The top of the 2 level stream table is (at most) 128k entries big, and two high order allocations are required. One of __le64 which is programmed into the HW (1M), and one of struct arm_smmu_strtab_l1_desc which holds the CPU pointer (3M). There is no reason to store the l2ptr_dma as nothing reads it. devm stores a copy of it and the DMA memory will be freed via devm mechanisms. span is a constant of 8+1. Remove both. This removes 16 bytes from each arm_smmu_l1_ctx_desc and saves up to 2M of memory per iommu instance. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 +++++++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 --- 2 files changed, 7 insertions(+), 10 deletions(-)