From patchwork Tue Feb 2 13:29:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF0A3C433DB for ; Tue, 2 Feb 2021 13:31:17 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 777BA64DBD for ; Tue, 2 Feb 2021 13:31:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 777BA64DBD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/WJkz0YhGMU1tg95bEl/eJGLiUD6fu/aTIQPHhwOC88=; b=k6A5RWme6E6G5fgCiM/ff/UvD dhlzqbYhB3sX2F/yAbae86KhW+tFSnlsOzP2d15m7VzzFRvkYai6lXm0NNIttab4es5FqkivcN9ef SQTvxcUBjUMa6bUfoRgWSg3vGEJ/OuCekp7OT0C8ZXOxfKSWJ/oZbnHimEd5gTaq2/WAOK6VEfJKI YxBVr9RY3vRTt6W8q9dC60clIXgppv4dsxMJn6Is9QkWiNTd7zMRwbFeh6ZXB7TNY8cn9Sk84bEV9 NhLLA4wmjsv+92VeYUP0sOfzaZUP2fYcBj/VTsZQQCf2s/I2NpUpmcUylF4/RUelIFwgcXZqrbnZ4 o6X+qes4A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6vku-0000XP-AG; Tue, 02 Feb 2021 13:30:08 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6vkp-0000Se-1F for linux-arm-kernel@lists.infradead.org; Tue, 02 Feb 2021 13:30:06 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id E2C3F64F68; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=0k8G1hBpz4Np2I1ZDNqtU5gVCYWWxmCauHG4Ld/0WK8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4qfx5bMt2weX0iSbqs43jbBq7MKFCkC+FAJ01PO13+R8QCwYAebtYke1AoVPZk9x bZuEFcOZHpH+IiAsJI1oTiGuJi6ou9tmvb1lV4y9zEWI0HOixjPBw9XQNYfDbNJeZy aMhJkU15oINMOcElK36EbUDelf3C/SLz4UIaNbg6RJgrIDxOlYIIIrcSgM/t/ATC9l 9BBrR5GqhEHcxfONkpUSkWOTUgoR89XtR2VJvNGRHnjzYKlxLHvQm4TzF1fDtokOvd Kt5epQ4fiFS4iuE9AC2T9ql1IiZcBs+kpLmjjh6C2jOmDQWuX5H9/rEjjETWRR53sD 5TJxwRQP/HImA== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011yv-KY; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab To: Subject: [PATCH 05/13] arm64: dts: hisilicon: Add HI3670 PCI-E controller support Date: Tue, 2 Feb 2021 14:29:50 +0100 Message-Id: <301bbde15f7a248222745c8ab98c0e20ae877db0.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210202_083003_382778_3D9E2872 X-CRM114-Status: GOOD ( 10.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, Wei Xu , Rob Herring , Manivannan Sadhasivam , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Manivannan Sadhasivam Add PCI-E controller support for HiSilicon HI3670 SoC. [mchehab+huawei@kernel.org: fix merge conflicts] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 64 +++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 5522a5de07a8..c0a0336a8ea4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,64 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie", "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xfc000000 0x0 0x80000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + switch,reset-gpios = <&gpio7 0 0 >; + eth,reset-gpios = <&gpio25 2 0 >; + m_2,reset-gpios = <&gpio3 1 0 >; + mini1,reset-gpios = <&gpio27 4 0 >; + + eth,clkreq-gpios = <&gpio20 6 0 >; + m_2,clkreq-gpios = <&gpio27 3 0 >; + mini1,clkreq-gpios = <&gpio17 0 0 >; + + /*vboost iboost pre post main*/ + eye_param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq_pmx_func &pcie_clkreq_cfg_func>; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";