From patchwork Mon Aug 10 12:22:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 11707363 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05918739 for ; Mon, 10 Aug 2020 12:22:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D32492070B for ; Mon, 10 Aug 2020 12:22:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EVX/A2ZE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D32492070B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=collabora.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=WHOL7HRvoOvC6HM3u7rbpGjsc64eQFDunvK/tEVTqec=; b=EVX/A2ZEFwNiZMObe0RZy2+M4 xBY5/7wyVjs8QQ110zOqQCD1kLrqysOBnoIPaAuTc7YXdQXvD4WkMfmVnOEYO+TRCK9zF0o+NL2m3 0p7+iw/BFNlEem1zUsGh3CoHd7xkTbvmbgsJVn115E+gft11Xb9SFowvbdy5JAn3sE9ZYDQkAs8eP NAdMU5Dq/AdAlkxpZ4SchnSbrHhlPPI0ivLzMgtz+2ElODvZVbbZeNVi7XHjXfBtTpeAiXsZw8AuC qJoonu2sYu1UYC4EsnM3DQsdDOGhlzk9yylr2x9SMaa0ZxjffUmG/YUIYk+fWYYKum/kHnRy0urVE I7v1Uidvg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k56ov-0001TZ-IH; Mon, 10 Aug 2020 12:22:30 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k56os-0001SB-1C for linux-arm-kernel@lists.infradead.org; Mon, 10 Aug 2020 12:22:27 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gtucker) with ESMTPSA id C26AD293510 From: Guillaume Tucker To: Russell King , Kukjin Kim , Krzysztof Kozlowski , Rob Herring Subject: [PATCH v2 3/4] ARM: dts: exynos: add prefetch properties for L2C-310 cache Date: Mon, 10 Aug 2020 13:22:07 +0100 Message-Id: <30cb8edca2185241471ee1318b05288900652521.1597061474.git.guillaume.tucker@collabora.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <267a81e550a0b5d479c82b5908e2a2caa4c9c874.1597061474.git.guillaume.tucker@collabora.com> References: <267a81e550a0b5d479c82b5908e2a2caa4c9c874.1597061474.git.guillaume.tucker@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200810_082226_177546_EF351A62 X-CRM114-Status: GOOD ( 13.25 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, kernel@collabora.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add the devicetree properties to enable instruction and data prefetch on exynos4210 and exynos4412 which use the L2C-310 cache. No other Exynos chip appears to be using this L2 cache hardware. This follows the default bits being set in the l2c_aux_val register for the Exynos platform, which can now be cleared as a result. Signed-off-by: Guillaume Tucker --- Notes: v2: split patch to include devicetree changes only arch/arm/boot/dts/exynos4210.dtsi | 2 ++ arch/arm/boot/dts/exynos4412.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b4466232f0c1..7e0d253b26ef 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -102,6 +102,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <2 2 1>; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 48868947373e..37efa247bf4d 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -218,6 +218,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <3 2 1>; arm,double-linefill = <1>;