From patchwork Wed Oct 27 07:19:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12586501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE887C433EF for ; Wed, 27 Oct 2021 07:21:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9071660F9B for ; Wed, 27 Oct 2021 07:21:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9071660F9B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UfoDFRsXXbiYOBd4euuYWxxrH00wbiNalNlxn99CXCc=; b=cBY+FJ5cajKKxp fxgBkyRvGe9QDADF++/TDOflVeVXjL5I15YbIe5uqeeQtq06JkHo69CIt284mHwUC1z40GW6eBg+3 UdRetpG3OwoNx1PvnbkTawhN1d1yXVlBG726ZLFczst0v3vkAyCCut4OG8UduKhWSpZUO2cnupsU1 A7JQzDDs3VpIxI1VTCKAmc4EXYnuwVPl5JFUXju6LwU/Kc5l+5WuBJQ1KSSR6ZF9MdT2KIuW7PfxV JoxF2Nmh1MR2hfzMBxKnbTKLftz4p0kbgdDhwxFzO8ACrRv+K8NRnCC9qX91v58b2i5/fbvSBvkLR gcwgK7ttliatiKSl+4BA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mfdE9-0048Gn-2T; Wed, 27 Oct 2021 07:20:01 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mfdDj-0048BJ-T4 for linux-arm-kernel@lists.infradead.org; Wed, 27 Oct 2021 07:19:47 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3EA91610A5; Wed, 27 Oct 2021 07:19:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635319175; bh=KG+yrRn87gJ/zy26fF8MDJvZ9hRK+FQIaH3IMKbElLU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SkR7iVHfbOIuRTWm/a/xF6/T5I1pdLAGtl1fEfkptGuValVaqQ+hkwBQUhlyD9XEy 17A0Kp/kAmyRl31jlhvnWQCRJqhSg15hm36uHYWV/Cy4TwCCllV886t45ci9lDO+/0 aH0uqxxDayyMzomGEX4klS3RFrhv+mGdTnuORFzylRa2bFhhUkTYSUAWWjh6PZWYTn LLtVgF7uqZysNrskuCmljfCNgrfLGdmH8NCjK+Mfy0WF9yt3wknRh9VuWo6u0F47fj XpOUyS6RJpSYj9ZeapclbG0RCv5T2SX77seIxonfQcV1WrSWSyiKQmKh1/eykrDv1b sY1396rUNZpVg== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1mfdDg-00CV5L-Kd; Wed, 27 Oct 2021 08:19:32 +0100 From: Mauro Carvalho Chehab To: Wei Xu Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH 1/1] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Date: Wed, 27 Oct 2021 08:19:25 +0100 Message-Id: <327bf452173f6b4e10f7ad875802884d9e8109a9.1635318674.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211027_001936_081856_185E54DE X-CRM114-Status: GOOD ( 12.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Manivannan Sadhasivam Add DTS bindings for the HiKey 970 board's PCIe hardware. Co-developed-by: Mauro Carvalho Chehab Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- To mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH 0/1] at: https://lore.kernel.org/all/cover.1635318674.git.mchehab+huawei@kernel.org/ arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 107 ++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 20698cfd0637..78b41336c587 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -659,6 +665,107 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", + "aclk"; + + /* vboost iboost pre post main */ + hisilicon,eye-diagram-param = <0xffffffff 0xffffffff + 0xffffffff 0xffffffff + 0xffffffff>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0>; + hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, + <&gpio20 6 0>; + pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0 + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@0,0 { // Lane 0: upstream + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@1,0 { // Lane 4: M.2 + reg = <0x0800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio3 1 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pcie@5,0 { // Lane 5: Mini PCIe + reg = <0x2800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio27 4 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pcie@7,0 { // Lane 6: Ethernet + reg = <0x3800 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio25 2 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";