From patchwork Sun Sep 8 17:32:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 13795582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3833DCD4F4C for ; Sun, 8 Sep 2024 17:35:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xh5qkc0c1+MDM8uSvx3tNtBQFpLWdYTXf/RSsVtEdy4=; b=SCtgZTJfsO63GgT4l7nXoisjQ8 XAQYYmxI7Z2chuDLgma5fLyligDcLIRV+GaVYJft23N+FmzjoIYltDx4Ujus9v0eX6qj29oyHd1i0 edjohKeid5/M6gmR43ozUclW+FTiiLd/zUtU9+iOOdwz+RTAG478eCDjfY+/7uJIyVKb9C5/Se0kt ZMHxHctwIRzuJ6HeFqODgUgRcQxJ7oMgCII7UZDGZvyG8TEAfzTQceENf3bQF+lTJeZT8SKkprxZx uE3noEPMGaIl5zdpQOAuSl/BHdKcLEjKRfqeOMloiQN9KYLLkfZqT1Kf0EKxkY8rYWlLXqo43RW8V +SSGPsOA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1snLpC-0000000HBeL-0d7u; Sun, 08 Sep 2024 17:35:46 +0000 Received: from mta-65-225.siemens.flowmailer.net ([185.136.65.225]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1snLmD-0000000HAyY-00Kx for linux-arm-kernel@lists.infradead.org; Sun, 08 Sep 2024 17:32:45 +0000 Received: by mta-65-225.siemens.flowmailer.net with ESMTPSA id 20240908173236156b4938718c549506 for ; Sun, 08 Sep 2024 19:32:37 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=xh5qkc0c1+MDM8uSvx3tNtBQFpLWdYTXf/RSsVtEdy4=; b=ibJ98p/xG9+0uKRwbXrpftDDuC3NOwllC2IbqCSkizfOqjw3ImVvbkdLNsMVEIuTfH+Xkr EyddHfiXA5PkIqwfFYC363dKbq/hKMK8fc5HAHRPDJQsvjrASOlT9lecE9pDabwzLgMEgZKr Ip/jKF6OcqPnn/JfLboBTXF55s5ylKGAsfJbeotcnwPDf/e5Nw+vfq43I/+tgwgk/2pS8BFI AsvUXcZwv6+P4zVc5sW5pgQeRNRo5bqGgc2S+JhffeQVTGFH/np32q50iW/5Gp78SdmcNcQZ a+Gre+vZlf5IBW4/bA9b2uEwzmpVOpKlWn8RcsMxNd/chbqQ6zHNv+iw==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas Subject: [PATCH v5 2/7] dt-bindings: PCI: ti,am65: Extend for use with PVU Date: Sun, 8 Sep 2024 19:32:28 +0200 Message-ID: <33d08f61fe9bd692da0eceab91209832bf16e804.1725816753.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240908_103241_483523_32A83E88 X-CRM114-Status: GOOD ( 13.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jan Kiszka The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices to specific regions of host memory. Add the optional property "memory-regions" to point to such regions of memory when PVU is used. Since the PVU deals with system physical addresses, utilizing the PVU with PCIe devices also requires setting up the VMAP registers to map the Requester ID of the PCIe device to the CBA Virtual ID, which in turn is mapped to the system physical address. Hence, describe the VMAP registers which are optional unless the PVU shall be used for PCIe. Signed-off-by: Jan Kiszka --- CC: Lorenzo Pieralisi CC: "Krzysztof Wilczyński" CC: Bjorn Helgaas CC: linux-pci@vger.kernel.org --- .../bindings/pci/ti,am65-pci-host.yaml | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 0a9d10532cc8..0c297d12173c 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -20,14 +20,18 @@ properties: - ti,keystone-pcie reg: - maxItems: 4 + minItems: 4 + maxItems: 6 reg-names: + minItems: 4 items: - const: app - const: dbics - const: config - const: atu + - const: vmap_lp + - const: vmap_hp interrupts: maxItems: 1 @@ -83,13 +87,30 @@ if: compatible: enum: - ti,am654-pcie-rc + then: + properties: + memory-region: + maxItems: 1 + description: | + phandle to a restricted DMA pool to be used for all devices behind + this controller. The regions should be defined according to + reserved-memory/shared-dma-pool.yaml. + required: - dma-coherent - power-domains - msi-map - num-viewport +else: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 + unevaluatedProperties: false examples: @@ -104,8 +125,10 @@ examples: reg = <0x5500000 0x1000>, <0x5501000 0x1000>, <0x10000000 0x2000>, - <0x5506000 0x1000>; - reg-names = "app", "dbics", "config", "atu"; + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; + reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; #size-cells = <2>;