From patchwork Sun Feb 4 06:59:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13544523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE84BC4828F for ; Sun, 4 Feb 2024 07:01:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OVSmTOuzz0QD8mwD4TlrHGFTjoZH7FGRsX1ed6XzNbg=; b=Q6ymTToBNR5YyO JHahYc1g7Jp9K/4A9j0tO9nNhDvrujVkcx8sVCwyl1TRuASRhdeGkNeiaYWvEbyPyITBrCYme6j1a pGR29/t5Nfxho4eUQ7lVSQwdbtdjYoJxfyzP+gm+nQcxYVA1OwS5ddBdNurW29kB0uTP5PFCUleCA bvWeLGyk5CvTMCpHO+m9yL/7L4m9fg29zXhLivD2fRQz8GCOSHuNqgEIddGq0+0NYBqJ/c6VX9F1A Q0fYYk9maYO68g/VYPkpahXQ8Iz3ZqlOXuiugjQ16obg6KMo68nCOOyIvN2+fQV/gmp/ScmSkkawQ byJ2BxHFVV0n56qlzUgQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rWWUo-00000000Hi6-0FNe; Sun, 04 Feb 2024 07:00:54 +0000 Received: from smtp-out1.suse.de ([2a07:de40:b251:101:10:150:64:1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rWWTw-00000000H0Q-0On8; Sun, 04 Feb 2024 07:00:02 +0000 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 3240921DF4; Sun, 4 Feb 2024 06:59:55 +0000 (UTC) Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 190AB1338E; Sun, 4 Feb 2024 06:59:55 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id ojjIA+s1v2WWZwAAD6G6ig (envelope-from ); Sun, 04 Feb 2024 06:59:55 +0000 From: Andrea della Porta To: Vinod Koul , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , dmaengine@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Maxime Ripard , Dom Cobley , Phil Elwell , Andrea della Porta Subject: [PATCH 12/12] bcm2835-dma: Fixes for dma_abort Date: Sun, 4 Feb 2024 07:59:40 +0100 Message-ID: <3d0dcc017339f7a78cd9840103db75f5be4034c6.1706948717.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Authentication-Results: smtp-out1.suse.de; none X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Queue-Id: 3240921DF4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240203_230000_398542_3633D75F X-CRM114-Status: GOOD ( 20.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Dom Cobley There is a problem with the current abort scheme when dma is blocked on a DREQ which prevents halting. This is triggered by SPI driver which aborts dma in this state and so leads to a halt timeout. Discussion with Broadcom suggests the sequence: CS.ACTIVE=0 while (CS.OUTSTANDING_TRANSACTIONS == 0) wait() DEBUG.RESET=1 should be safe on a dma40 channel. Unfortunately the non-dma40 channels don't have OUTSTANDING_TRANSACTIONS, so we need a more complicated scheme. We attempt to abort the channel, which will work if there is no blocked DREQ. It it times out, we can assume there is no AXI transfer in progress and reset anyway. The length of the timeout is observed at ~20us. Signed-off-by: Dom Cobley Signed-off-by: Andrea della Porta --- drivers/dma/bcm2835-dma.c | 72 +++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 33 deletions(-) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c index 40df0a165992..5751d1c6ff94 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c @@ -245,6 +245,7 @@ struct bcm2835_desc { #define BCM2711_DMA40_ERR BIT(10) #define BCM2711_DMA40_QOS(x) (((x) & 0x1f) << 16) #define BCM2711_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20) +#define BCM2711_DMA40_TRANSACTIONS BIT(25) #define BCM2711_DMA40_WAIT_FOR_WRITES BIT(28) #define BCM2711_DMA40_DISDEBUG BIT(29) #define BCM2711_DMA40_ABORT BIT(30) @@ -671,30 +672,37 @@ static void bcm2835_dma_fill_cb_chain_with_sg( static void bcm2835_dma_abort(struct bcm2835_chan *c) { void __iomem *chan_base = c->chan_base; - long int timeout = 10000; - - /* - * A zero control block address means the channel is idle. - * (The ACTIVE flag in the CS register is not a reliable indicator.) - */ - if (!readl(chan_base + BCM2835_DMA_ADDR)) - return; + long timeout = 100; if (c->is_40bit_channel) { - /* Halt the current DMA */ - writel(readl(chan_base + BCM2711_DMA40_CS) | BCM2711_DMA40_HALT, + /* + * A zero control block address means the channel is idle. + * (The ACTIVE flag in the CS register is not a reliable indicator.) + */ + if (!readl(chan_base + BCM2711_DMA40_CB)) + return; + + /* Pause the current DMA */ + writel(readl(chan_base + BCM2711_DMA40_CS) & ~BCM2711_DMA40_ACTIVE, chan_base + BCM2711_DMA40_CS); - while ((readl(chan_base + BCM2711_DMA40_CS) & BCM2711_DMA40_HALT) && --timeout) + /* wait for outstanding transactions to complete */ + while ((readl(chan_base + BCM2711_DMA40_CS) & BCM2711_DMA40_TRANSACTIONS) && + --timeout) cpu_relax(); - /* Peripheral might be stuck and fail to halt */ + /* Peripheral might be stuck and fail to complete */ if (!timeout) dev_err(c->vc.chan.device->dev, - "failed to halt dma\n"); + "failed to complete pause on dma %d (CS:%08x)\n", c->ch, + readl(chan_base + BCM2711_DMA40_CS)); + /* Set CS back to default state */ writel(BCM2711_DMA40_PROT, chan_base + BCM2711_DMA40_CS); - writel(0, chan_base + BCM2711_DMA40_CB); + + /* Reset the DMA */ + writel(readl(chan_base + BCM2711_DMA40_DEBUG) | BCM2711_DMA40_DEBUG_RESET, + chan_base + BCM2711_DMA40_DEBUG); } else { /* * A zero control block address means the channel is idle. @@ -703,20 +711,6 @@ static void bcm2835_dma_abort(struct bcm2835_chan *c) if (!readl(chan_base + BCM2835_DMA_ADDR)) return; - /* Write 0 to the active bit - Pause the DMA */ - writel(readl(chan_base + BCM2835_DMA_CS) & ~BCM2835_DMA_ACTIVE, - chan_base + BCM2835_DMA_CS); - - /* wait for DMA to be paused */ - while ((readl(chan_base + BCM2835_DMA_CS) & BCM2835_DMA_WAITING_FOR_WRITES) && - --timeout) - cpu_relax(); - - /* Peripheral might be stuck and fail to signal AXI write responses */ - if (!timeout) - dev_err(c->vc.chan.device->dev, - "failed to pause dma\n"); - /* We need to clear the next DMA block pending */ writel(0, chan_base + BCM2835_DMA_NEXTCB); @@ -724,15 +718,27 @@ static void bcm2835_dma_abort(struct bcm2835_chan *c) writel(readl(chan_base + BCM2835_DMA_CS) | BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, chan_base + BCM2835_DMA_CS); - /* wait for DMA to have been aborted */ - timeout = 10000; + /* wait for DMA to be aborted */ while ((readl(chan_base + BCM2835_DMA_CS) & BCM2835_DMA_ABORT) && --timeout) cpu_relax(); - /* Peripheral might be stuck and fail to signal AXI write responses */ - if (!timeout) + /* Write 0 to the active bit - Pause the DMA */ + writel(readl(chan_base + BCM2835_DMA_CS) & ~BCM2835_DMA_ACTIVE, + chan_base + BCM2835_DMA_CS); + + /* + * Peripheral might be stuck and fail to complete + * This is expected when dreqs are enabled but not asserted + * so only report error in non dreq case + */ + if (!timeout && !(readl(chan_base + BCM2835_DMA_TI) & + (BCM2835_DMA_S_DREQ | BCM2835_DMA_D_DREQ))) dev_err(c->vc.chan.device->dev, - "failed to abort dma\n"); + "failed to complete pause on dma %d (CS:%08x)\n", c->ch, + readl(chan_base + BCM2835_DMA_CS)); + + /* Set CS back to default state and reset the DMA */ + writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS); } }