Message ID | 3d11015512a085592f2aca76eeddc04178d38bbe.1611232558.git.michal.simek@xilinx.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | arm64: dts: zynqmp: Enable and Wire DP | expand |
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 3ca7e4ee51b5..c676afc95f6d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -227,3 +227,7 @@ &watchdog0 { &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; + +&zynqmp_dpdma { + clocks = <&zynqmp_clk DPDMA_REF>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 66d53521ec58..f12cd24adbee 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -847,5 +847,15 @@ lpd_watchdog: watchdog@ff150000 { reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; + + zynqmp_dpdma: dma-controller@fd4c0000 { + compatible = "xlnx,zynqmp-dpdma"; + status = "disabled"; + reg = <0x0 0xfd4c0000 0x0 0x1000>; + interrupts = <0 122 4>; + interrupt-parent = <&gic>; + clock-names = "axi_clk"; + #dma-cells = <1>; + }; }; };