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Tue, 06 Feb 2018 01:28:49 -0800 (PST) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id t16sm18618429pfh.131.2018.02.06.01.28.45 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 01:28:48 -0800 (PST) From: Baolin Wang To: robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, arnd@arndb.de Subject: [PATCH 1/7] arm64: dts: Add hwspinlock node for Spreadtrum SC9860 Date: Tue, 6 Feb 2018 17:28:20 +0800 Message-Id: <410b2f2d3f3f019c96ec31213647c41cd7f1174d.1517908478.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, orson.zhai@spreadtrum.com, mathieu.poirier@linaro.org, baolin.wang@linaro.org, linux-kernel@vger.kernel.org, broonie@kernel.org, chunyan.zhang@spreadtrum.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Spreadtrum SC9860 platform only has one hardware spinlock device, which is located on AON system of Spreadtrum SC9860 platform. Signed-off-by: Baolin Wang --- arch/arm64/boot/dts/sprd/whale2.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 328009c..b9cc0fb 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -6,6 +6,8 @@ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#include + / { interrupt-parent = <&gic>; #address-cells = <2>; @@ -104,6 +106,21 @@ status = "disabled"; }; }; + + aon { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hwlock: hwspinlock@40500000 { + compatible = "sprd,hwspinlock-r3p0"; + reg = <0 0x40500000 0 0x1000>; + #hwlock-cells = <1>; + clock-names = "enable"; + clocks = <&aon_gate CLK_SPLK_EB>; + }; + }; }; ext_32k: ext_32k {