From patchwork Fri Aug 4 12:06:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honghui Zhang X-Patchwork-Id: 9881131 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9290C6031B for ; Fri, 4 Aug 2017 12:09:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 68D82289DA for ; Fri, 4 Aug 2017 12:09:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5D403289E1; Fri, 4 Aug 2017 12:09:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_NONE, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C2831289DD for ; Fri, 4 Aug 2017 12:09:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jaAZ2v6DFXGaJQbq7QGw7paTo9wrhrnfcIf6HbzqYGw=; b=p1jlU13FsRAYnP OZf0MOIcPucbx2H+CSqbb27M+VCjk3tSUDkicdnSlBSO2uzblX8lElIIl4L/Y/6vVgGiuXYwaf842 WRCQtEktApKRn4LLpPNOly6FIkR98PhsYy1YTpIOZ6+SZNxAcjBBpcm5Lm0qz1dWce2ue9px65LGu O1WtmirJNslJvtbcdprnJHt5ohgB/NALMT3ERrCvevO9ZLpDPShBdj6nvFRNBoEqkqTWVNmHlodfi gOV/V4HYhh8mvBKGK4msLpQCzoW6m4h1KYzt8nnlXmEBUbT+xz7VW/Qc2LzVZdA/LuFc7vsX7Z1qA 07iXfk7nvrN60wUhSzNQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ddbPa-0008FT-KE; Fri, 04 Aug 2017 12:09:02 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1ddbNu-0006bH-9L; Fri, 04 Aug 2017 12:07:27 +0000 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1653843298; Fri, 04 Aug 2017 20:06:51 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 4 Aug 2017 20:06:50 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 4 Aug 2017 20:06:49 +0800 From: To: , , , , , , , , , , , Subject: [PATCH v3 4/6] dt-bindings: PCI: rename and cleanup MediaTek binding text Date: Fri, 4 Aug 2017 20:06:40 +0800 Message-ID: <4209148bf2fa9bb981d44e8b0245141ccb25c23a.1501846816.git.honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170804_050718_852424_0D61C4C0 X-CRM114-Status: UNSURE ( 9.42 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, hongkun.cao@mediatek.com, sean.wang@mediatek.com, xinping.qian@mediatek.com, honghui.zhang@mediatek.com, yt.shen@mediatek.com, yong.wu@mediatek.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ryder Lee In order to accommodate other SoC generations, this patch updates filename to make it more generic, regroups specific properties by SoCs, and removes redundant descriptions. Signed-off-by: Ryder Lee Signed-off-by: Honghui Zhang Acked-by: Rob Herring --- ...{mediatek,mt7623-pcie.txt => mediatek-pcie.txt} | 32 +++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) rename Documentation/devicetree/bindings/pci/{mediatek,mt7623-pcie.txt => mediatek-pcie.txt} (90%) diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt similarity index 90% rename from Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt rename to Documentation/devicetree/bindings/pci/mediatek-pcie.txt index fe80dda..0fdcb15 100644 --- a/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -1,18 +1,13 @@ -MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs - -PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root -ports supports a Gen2 1-lane Link and has PIPE interface to PHY. +MediaTek Gen2 PCIe controller Required properties: -- compatible: Should contain "mediatek,mt7623-pcie". +- compatible: Should contain one of the following strings: + "mediatek,mt2701-pcie" + "mediatek,mt7623-pcie" - device_type: Must be "pci" - reg: Base addresses and lengths of the PCIe controller. - #address-cells: Address representation for root ports (must be 3) - #size-cells: Size representation for root ports (must be 2) -- #interrupt-cells: Size representation for interrupts (must be 1) -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties - Please refer to the standard PCI bus binding document for a more detailed - explanation. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: @@ -20,12 +15,6 @@ Required properties: - sys_ck0 :for clock of Port0 - sys_ck1 :for clock of Port1 - sys_ck2 :for clock of Port2 -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - pcie-rst0 :port0 reset - - pcie-rst1 :port1 reset - - pcie-rst2 :port2 reset - phys: List of PHY specifiers (used by generic PHY framework). - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property. @@ -34,6 +23,16 @@ Required properties: - bus-range: Range of bus numbers associated with this controller. - ranges: Ranges for the PCI memory and I/O regions. +Required properties for MT7623/MT2701: +- #interrupt-cells: Size representation for interrupts (must be 1) +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the + number of root ports. + In addition, the device tree node must have sub-nodes describing each PCIe port interface, having the following mandatory properties: @@ -85,7 +84,8 @@ Examples: <&hifsys MT2701_HIFSYS_PCIE1_RST>, <&hifsys MT2701_HIFSYS_PCIE2_RST>; reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; - phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>; + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, + <&pcie2_phy PHY_TYPE_PCIE>; phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; bus-range = <0x00 0xff>;