From patchwork Thu Mar 30 15:23:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 9654507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7E817602BD for ; Thu, 30 Mar 2017 15:26:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F85A2850F for ; Thu, 30 Mar 2017 15:26:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6251F28555; Thu, 30 Mar 2017 15:26:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B5C142850F for ; Thu, 30 Mar 2017 15:26:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=5bIyivnsZT51yCp8l24BW2vy+kfS2DV5WbBFO/Iit9o=; b=hLDJPqw+svggajE0d0Xu4tK8Z/ 7HOh6VBY0EJgZMQk4NPexs8TewrHVev6/WOoQebc5F+JaEQ1lLjI0yCILoWxnFsloWafgfE9QikCj bR/7trXFZgNweSz/fgbfNHrcfcRt4PfMluXICRqZoIXzUJ7kcOqP3kd/eLomjAfcuur8ZTcNA7lrj DrfuOkbK5UwfnNETyhV6a0rd1j354qrLAaaB9QJvAnQlMlT2drNxheOsuAJqpIVJfSC5y8r4XVVrV HUoj7eDa74DKkomFBBox/uZAK994CZZIQM8gkOFOAnxHYuzJroGbCl0rsXjdtdtS1MSd+93aNeJ7Q sPRDXrIg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ctbxb-00005K-Tt; Thu, 30 Mar 2017 15:26:04 +0000 Received: from mail.free-electrons.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ctbvi-0004wH-AW for linux-arm-kernel@lists.infradead.org; Thu, 30 Mar 2017 15:24:15 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id D537E2081F; Thu, 30 Mar 2017 17:23:26 +0200 (CEST) Received: from localhost (83.146.29.93.rev.sfr.net [93.29.146.83]) by mail.free-electrons.com (Postfix) with ESMTPSA id BC27920BB8; Thu, 30 Mar 2017 17:23:10 +0200 (CEST) From: Gregory CLEMENT To: Ulf Hansson , Adrian Hunter , linux-mmc@vger.kernel.org Subject: [PATCH v7 09/13] mmc: sdhci-xenon: Add SoC PHY PAD voltage control Date: Thu, 30 Mar 2017 17:23:01 +0200 Message-Id: <4363b2b62cd424745ebc2e630d30dad968814e46.1490886907.git-series.gregory.clement@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170330_082407_612553_E49021E6 X-CRM114-Status: GOOD ( 17.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jimmy Xu , Andrew Lunn , Mike Turquette , Nadav Haklai , Ziji Hu , Victor Gu , Doug Jones , linux-clk@vger.kernel.org, Jisheng Zhang , Yehuda Yitschak , Marcin Wojtas , Kostya Porotchkin , Hanna Hawa , Sebastian Hesselbarth , devicetree@vger.kernel.org, Jason Cooper , Rob Herring , Ryan Gao , Gregory CLEMENT , "Wei\(SOCP\) Liu" , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Stephen Boyd , linux-kernel@vger.kernel.org, Wilson Ding MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Hu Ziji Some SoCs have PHY PAD outside Xenon IP. PHY PAD voltage should match signalling voltage in use. Add generic SoC PHY PAD voltage control interface. Implement Aramda-3700 SoC PHY PAD voltage control. Signed-off-by: Hu Ziji Tested-by: Russell King Signed-off-by: Gregory CLEMENT --- drivers/mmc/host/sdhci-xenon-phy.c | 110 +++++++++++++++++++++++++++++- drivers/mmc/host/sdhci-xenon.c | 2 +- drivers/mmc/host/sdhci-xenon.h | 2 +- 3 files changed, 113 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index b14544e91b65..4bdbcd3f2645 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -143,6 +143,21 @@ enum xenon_phy_type_enum { NR_PHY_TYPES }; +enum soc_pad_ctrl_type { + SOC_PAD_SD, + SOC_PAD_FIXED_1_8V, +}; + +struct soc_pad_ctrl { + /* Register address of SoC PHY PAD ctrl */ + void __iomem *reg; + /* SoC PHY PAD ctrl type */ + enum soc_pad_ctrl_type pad_type; + /* SoC specific operation to set SoC PHY PAD */ + void (*set_soc_pad)(struct sdhci_host *host, + unsigned char signal_voltage); +}; + static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = { .timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST, .func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL, @@ -176,6 +191,8 @@ struct xenon_emmc_phy_params { u8 nr_tun_times; /* Divider for calculating Tuning Step */ u8 tun_step_divider; + + struct soc_pad_ctrl pad_ctrl; }; static int xenon_alloc_emmc_phy(struct sdhci_host *host) @@ -254,6 +271,45 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) return 0; } +#define ARMADA_3700_SOC_PAD_1_8V 0x1 +#define ARMADA_3700_SOC_PAD_3_3V 0x0 + +static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host, + unsigned char signal_voltage) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); + struct xenon_emmc_phy_params *params = priv->phy_params; + + if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) { + writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); + } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) { + if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) + writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); + else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) + writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg); + } +} + +/* + * Set SoC PHY voltage PAD control register, + * according to the operation voltage on PAD. + * The detailed operation depends on SoC implementation. + */ +static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host, + unsigned char signal_voltage) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); + struct xenon_emmc_phy_params *params = priv->phy_params; + + if (!params->pad_ctrl.reg) + return; + + if (params->pad_ctrl.set_soc_pad) + params->pad_ctrl.set_soc_pad(host, signal_voltage); +} + /* * Enable eMMC PHY HW DLL * DLL should be enabled and stable before HS200/SDR104 tuning, @@ -562,6 +618,51 @@ static void xenon_emmc_phy_set(struct sdhci_host *host, dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n"); } +static int get_dt_pad_ctrl_data(struct sdhci_host *host, + struct device_node *np, + struct xenon_emmc_phy_params *params) +{ + int ret = 0; + const char *name; + struct resource iomem; + + if (of_device_is_compatible(np, "marvell,armada-3700-sdhci")) + params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set; + else + return 0; + + if (of_address_to_resource(np, 1, &iomem)) { + dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %s\n", + np->name); + return -EINVAL; + } + + params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc), + &iomem); + if (IS_ERR(params->pad_ctrl.reg)) { + dev_err(mmc_dev(host->mmc), "Unable to get SoC PHY PAD ctrl register for %s\n", + np->name); + return PTR_ERR(params->pad_ctrl.reg); + } + + ret = of_property_read_string(np, "marvell,pad-type", &name); + if (ret) { + dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n"); + return ret; + } + if (!strcmp(name, "sd")) { + params->pad_ctrl.pad_type = SOC_PAD_SD; + } else if (!strcmp(name, "fixed-1-8v")) { + params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V; + } else { + dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n", + name); + return -EINVAL; + } + + return ret; +} + static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host, struct device_node *np, struct xenon_emmc_phy_params *params) @@ -590,7 +691,14 @@ static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host, &value)) params->tun_step_divider = value & 0xFF; - return 0; + return get_dt_pad_ctrl_data(host, np, params); +} + +/* Set SoC PHY Voltage PAD */ +void xenon_soc_pad_ctrl(struct sdhci_host *host, + unsigned char signal_voltage) +{ + xenon_emmc_phy_set_soc_pad(host, signal_voltage); } /* diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c index 36e22bd2b8cc..8e56b9ccfb39 100644 --- a/drivers/mmc/host/sdhci-xenon.c +++ b/drivers/mmc/host/sdhci-xenon.c @@ -280,6 +280,8 @@ static int xenon_start_signal_voltage_switch(struct mmc_host *mmc, */ xenon_enable_internal_clk(host); + xenon_soc_pad_ctrl(host, ios->signal_voltage); + /* * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable. * Thus SDHCI_CTRL_VDD_180 bit might not work then. diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h index b29d45358de8..6e6523ea01ce 100644 --- a/drivers/mmc/host/sdhci-xenon.h +++ b/drivers/mmc/host/sdhci-xenon.h @@ -96,4 +96,6 @@ int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios); void xenon_clean_phy(struct sdhci_host *host); int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host); +void xenon_soc_pad_ctrl(struct sdhci_host *host, + unsigned char signal_voltage); #endif