From patchwork Wed Nov 7 14:37:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 1710671 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 12AA53FC8F for ; Wed, 7 Nov 2012 14:39:51 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TW6lC-0006lI-KR; Wed, 07 Nov 2012 14:37:42 +0000 Received: from mail-pb0-f49.google.com ([209.85.160.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TW6l7-0006k0-Im for linux-arm-kernel@lists.infradead.org; Wed, 07 Nov 2012 14:37:38 +0000 Received: by mail-pb0-f49.google.com with SMTP id xa7so1171056pbc.36 for ; Wed, 07 Nov 2012 06:37:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=DOpgBKBhIODSCXHabjcLd0t8oqoucoMDFfHRy2yqw7Y=; b=L6f7b2odCvwHfV6yshrHcSuVuQMnXstCoqFWinzwtaNHqfkI6DIoe5e6wTz4DPjUt3 vFLNYsdYSDl49oXPHOOUcdjXmjHYgp2eBT1ceBPkR2WBViKObNYnMyKzEYzIAJoF1uDL 7ckAGLXFxkn0Hy8funQAiSNgGDArGzf/T/jzUZVXM+RXN16CSVSjlXBmXWKD6VlJe1Yc X9myU1aVcEKmNNqBaun7mpOvaUBNvbFJG3U5emywqYoBPzG3xbs3/InpGLU2/RnMD3Cj YvDyAjIhBxcB438y/cbRiyIBt6psGRX9wBWmC+6sN8QbqPckQW6y2wLpYokqWIsd4B84 S6xA== Received: by 10.68.251.130 with SMTP id zk2mr14395699pbc.19.1352299052970; Wed, 07 Nov 2012 06:37:32 -0800 (PST) Received: from localhost ([122.167.84.139]) by mx.google.com with ESMTPS id mn5sm14227522pbc.12.2012.11.07.06.37.30 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Nov 2012 06:37:32 -0800 (PST) From: Viresh Kumar To: linus.walleij@linaro.org Subject: [PATCH] pinctrl: SPEAr: Add SoC specific gpio configuration routines Date: Wed, 7 Nov 2012 20:07:25 +0530 Message-Id: <440eeee0b362a9b2db3749a49c78b6aabdd5ad6a.1352298892.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 1.7.12.rc2.18.g61b472e X-Gm-Message-State: ALoCoQk3PEyZmN2DM8YynwhLbsS/1i9Ldb7GSeSiJN2pf+psIdiq4M/BL5eR9uxlQ8FWn8uGc60e X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121107_093737_913872_A14D9940 X-CRM114-Status: GOOD ( 16.70 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Shiraz Hashim , spear-devel@list.st.com, linux-arm-kernel@lists.infradead.org, Viresh Kumar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Shiraz Hashim Different SPEAr SoCs have different approach to configure pins as gpios. Some configure a group of gpios with single register bit and others have one bit per gpio pin. Only earlier one is implemented till now, this patch adds support for later one. Here we add callbacks to SoC specific code to configure gpios in gpio_request_enable(). That will do additional SoC specific configuration to enable gpio pins. We also implement this callback for SPEAr1340 in this patch. Signed-off-by: Shiraz Hashim Signed-off-by: Viresh Kumar --- drivers/pinctrl/spear/pinctrl-spear.c | 26 ++++++++++++-------------- drivers/pinctrl/spear/pinctrl-spear.h | 14 ++++++++++++++ drivers/pinctrl/spear/pinctrl-spear1340.c | 27 +++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index cbca6dc..f9483ae 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -29,16 +28,6 @@ #define DRIVER_NAME "spear-pinmux" -static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) -{ - return readl_relaxed(pmx->vbase + reg); -} - -static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) -{ - writel_relaxed(val, pmx->vbase + reg); -} - static void muxregs_endisable(struct spear_pmx *pmx, struct spear_muxreg *muxregs, u8 count, bool enable) { @@ -316,16 +305,25 @@ static int gpio_request_endisable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, bool enable) { struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + struct spear_pinctrl_machdata *machdata = pmx->machdata; struct spear_gpio_pingroup *gpio_pingroup; + /* + * Some SoC have configuration options applicable to group of pins, + * rather than a single pin. + */ gpio_pingroup = get_gpio_pingroup(pmx, offset); - if (IS_ERR(gpio_pingroup)) - return PTR_ERR(gpio_pingroup); - if (gpio_pingroup) muxregs_endisable(pmx, gpio_pingroup->muxregs, gpio_pingroup->nmuxregs, enable); + /* + * SoC may need some extra configurations, or configurations for single + * pin + */ + if (machdata->gpio_request_endisable) + machdata->gpio_request_endisable(pmx, offset, enable); + return 0; } diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h index 94f142c..b063327 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.h +++ b/drivers/pinctrl/spear/pinctrl-spear.h @@ -13,11 +13,13 @@ #define __PINMUX_SPEAR_H__ #include +#include #include #include struct platform_device; struct device; +struct spear_pmx; /** * struct spear_pmx_mode - SPEAr pmx mode @@ -155,6 +157,8 @@ struct spear_pinctrl_machdata { struct spear_pingroup **groups; unsigned ngroups; struct spear_gpio_pingroup *gpio_pingroups; + void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset, + bool enable); unsigned ngpio_pingroups; bool modes_supported; @@ -178,6 +182,16 @@ struct spear_pmx { }; /* exported routines */ +static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) +{ + return readl_relaxed(pmx->vbase + reg); +} + +static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) +{ + writel_relaxed(val, pmx->vbase + reg); +} + void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); void __devinit pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup, diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c index 0606b8c..0b4af0e 100644 --- a/drivers/pinctrl/spear/pinctrl-spear1340.c +++ b/drivers/pinctrl/spear/pinctrl-spear1340.c @@ -1971,6 +1971,32 @@ static struct spear_function *spear1340_functions[] = { &sata_function, }; +static void gpio_request_endisable(struct spear_pmx *pmx, int pin, + bool enable) +{ + unsigned int regoffset, regindex, bitoffset; + unsigned int val; + + /* pin++ as gpio configuration starts from 2nd bit of base register */ + pin++; + + regindex = pin / 32; + bitoffset = pin % 32; + + if (regindex <= 3) + regoffset = PAD_FUNCTION_EN_1 + regindex * sizeof(int *); + else + regoffset = PAD_FUNCTION_EN_5 + (regindex - 4) * sizeof(int *); + + val = pmx_readl(pmx, regoffset); + if (enable) + val &= ~(0x1 << bitoffset); + else + val |= 0x1 << bitoffset; + + pmx_writel(pmx, val, regoffset); +} + static struct spear_pinctrl_machdata spear1340_machdata = { .pins = spear1340_pins, .npins = ARRAY_SIZE(spear1340_pins), @@ -1978,6 +2004,7 @@ static struct spear_pinctrl_machdata spear1340_machdata = { .ngroups = ARRAY_SIZE(spear1340_pingroups), .functions = spear1340_functions, .nfunctions = ARRAY_SIZE(spear1340_functions), + .gpio_request_endisable = gpio_request_endisable, .modes_supported = false, };