From patchwork Tue Jul 25 15:26:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason X-Patchwork-Id: 9862297 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CA6256038F for ; Tue, 25 Jul 2017 15:28:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4CF01FFF9 for ; Tue, 25 Jul 2017 15:28:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B9A35204C1; Tue, 25 Jul 2017 15:28:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BE2DD1FFF9 for ; Tue, 25 Jul 2017 15:28:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:References:To:From:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+KJ3OE6NkMQ/SHchaAq0ZtrDS2xuVPw3x7a2p7uuO04=; b=UdFeX9watCuj/p NKM/9QkDRXqW5o7Q70sN8ALGgAzrQRa01nLdO6wAedTXubLzDZKKoh4iNVft+dM0w1QLCJlftseBh 8zr/thCc1+DAxE9OjEAFk8vFzdTkJUUWwEqT4Vkk15XvO23wl6S0Fbw0PgrNyqzAWN8S8oo9mY2lt Z0jgn937RpzikWVo7xDFyU53okzDn720EKVQGc3q3xPsMSBxtObuZFll0S9IRMATR6ayJDuWjI5jg M1LAcgOf/c1EgsNcbnu2FZ4pfGlqr+dwffacSwEctyVgNox4rBgfw0e9lRDkd6PwkzqLRUnk+bBpy D/9VHDBShFTETiqB9VoA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1da1km-0002Zz-Rw; Tue, 25 Jul 2017 15:28:08 +0000 Received: from smtp5-g21.free.fr ([2a01:e0c:1:1599::14]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1da1kA-00028N-D5 for linux-arm-kernel@lists.infradead.org; Tue, 25 Jul 2017 15:27:52 +0000 Received: from [172.27.0.114] (unknown [92.154.11.170]) (Authenticated sender: slash.tmp) by smtp5-g21.free.fr (Postfix) with ESMTPSA id D79935FF23; Tue, 25 Jul 2017 17:26:47 +0200 (CEST) Subject: [PATCH v5] irqchip: Add support for tango interrupt router From: Mason To: Marc Zyngier , Thomas Gleixner References: <657580dd-0cfe-e377-e425-0deabf6d20c3@free.fr> <20170606175219.34ef62b9@free-electrons.com> <24f34220-a017-f4e0-b72e-d1fdb014c0e1@free.fr> <9f384711-eef0-5117-b89c-9d2dc16e5ae5@free.fr> Message-ID: <473118cd-20dc-3534-d0d8-88799e3d2c3b@free.fr> Date: Tue, 25 Jul 2017 17:26:47 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Firefox/52.0 SeaMonkey/2.49.1 MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170725_082731_378449_8B39756E X-CRM114-Status: GOOD ( 18.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Petazzoni , Mark Rutland , Jason Cooper , Thibaud Cornic , LKML , Linux ARM Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This controller maps 128 input lines to 24 output lines. The output lines are routed to GIC SPI 0 to 23. This driver muxes LEVEL_HIGH IRQs onto output line 0, and gives every EDGE_RISING IRQ a dedicated output line. --- Changes from v4 to v5: - maz said "data->mask is definitely off limits. it is an internal data structure for the generic irqchip, and drivers have no business touching that." Use an array instead. --- .../interrupt-controller/sigma,smp8759-intc.txt | 18 +++ drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-smp8759.c | 174 +++++++++++++++++++++ 3 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sigma,smp8759-intc.txt create mode 100644 drivers/irqchip/irq-smp8759.c diff --git a/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8759-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8759-intc.txt new file mode 100644 index 000000000000..9ec922f3c0a4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sigma,smp8759-intc.txt @@ -0,0 +1,18 @@ +Sigma Designs SMP8759 interrupt router + +Required properties: +- compatible: "sigma,smp8759-intc" +- reg: address/size of register area +- interrupt-controller +- #interrupt-cells: <2> (hwirq and trigger_type) +- interrupt-parent: parent phandle + +Example: + + interrupt-controller@6f800 { + compatible = "sigma,smp8759-intc"; + reg = <0x6f800 0x430>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + }; diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e4dbfc85abdb..013104923b71 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -47,7 +47,7 @@ obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o obj-$(CONFIG_ST_IRQCHIP) += irq-st.o -obj-$(CONFIG_TANGO_IRQ) += irq-tango.o +obj-$(CONFIG_TANGO_IRQ) += irq-tango.o irq-smp8759.o obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o obj-$(CONFIG_TS4800_IRQ) += irq-ts4800.o obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o diff --git a/drivers/irqchip/irq-smp8759.c b/drivers/irqchip/irq-smp8759.c new file mode 100644 index 000000000000..2219c449b29e --- /dev/null +++ b/drivers/irqchip/irq-smp8759.c @@ -0,0 +1,174 @@ +#include +#include +#include +#include + +/* + * This controller maps IRQ_MAX input lines to SPI_MAX output lines. + * The output lines are routed to GIC SPI 0 to 23. + * This driver muxes LEVEL_HIGH IRQs onto output line 0, + * and gives every EDGE_RISING IRQ a dedicated output line. + */ +#define IRQ_MAX 128 +#define SPI_MAX 24 +#define LEVEL_SPI 0 +#define IRQ_ENABLE BIT(31) +#define STATUS 0x420 + +struct tango_intc { + void __iomem *base; + struct irq_domain *dom; + u8 spi_to_tango_irq[SPI_MAX]; + u8 tango_irq_to_spi[IRQ_MAX]; + DECLARE_BITMAP(enabled_level, IRQ_MAX); + spinlock_t lock; +}; + +static void tango_level_isr(struct irq_desc *desc) +{ + uint pos, virq; + struct irq_chip *chip = irq_desc_get_chip(desc); + struct tango_intc *intc = irq_desc_get_handler_data(desc); + DECLARE_BITMAP(status, IRQ_MAX); + + chained_irq_enter(chip, desc); + + spin_lock(&intc->lock); + memcpy_fromio(status, intc->base + STATUS, IRQ_MAX / BITS_PER_BYTE); + bitmap_and(status, status, intc->enabled_level, IRQ_MAX); + spin_unlock(&intc->lock); + + for_each_set_bit(pos, status, IRQ_MAX) { + virq = irq_find_mapping(intc->dom, pos); + generic_handle_irq(virq); + } + + chained_irq_exit(chip, desc); +} + +static void tango_edge_isr(struct irq_desc *desc) +{ + uint virq; + struct irq_data *data = irq_desc_get_irq_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct tango_intc *intc = irq_desc_get_handler_data(desc); + int tango_irq = intc->spi_to_tango_irq[data->hwirq - 32]; + + chained_irq_enter(chip, desc); + virq = irq_find_mapping(intc->dom, tango_irq); + generic_handle_irq(virq); + chained_irq_exit(chip, desc); +} + +static void tango_mask(struct irq_data *data) +{ + unsigned long flags; + struct tango_intc *intc = data->chip_data; + u32 spi = intc->tango_irq_to_spi[data->hwirq]; + + spin_lock_irqsave(&intc->lock, flags); + writel_relaxed(0, intc->base + data->hwirq * 4); + if (spi == LEVEL_SPI) + __clear_bit(data->hwirq, intc->enabled_level); + spin_unlock_irqrestore(&intc->lock, flags); +} + +static void tango_unmask(struct irq_data *data) +{ + unsigned long flags; + struct tango_intc *intc = data->chip_data; + u32 spi = intc->tango_irq_to_spi[data->hwirq]; + + spin_lock_irqsave(&intc->lock, flags); + writel_relaxed(IRQ_ENABLE | spi, intc->base + data->hwirq * 4); + if (spi == LEVEL_SPI) + __set_bit(data->hwirq, intc->enabled_level); + spin_unlock_irqrestore(&intc->lock, flags); +} + +static int tango_set_type(struct irq_data *data, uint flow_type) +{ + return 0; +} + +static struct irq_chip tango_chip = { + .name = "tango", + .irq_mask = tango_mask, + .irq_unmask = tango_unmask, + .irq_set_type = tango_set_type, +}; + +static int tango_alloc(struct irq_domain *dom, uint virq, uint n, void *arg) +{ + int spi; + struct irq_fwspec *fwspec = arg; + struct tango_intc *intc = dom->host_data; + u32 hwirq = fwspec->param[0], trigger = fwspec->param[1]; + + if (trigger & IRQ_TYPE_EDGE_FALLING || trigger & IRQ_TYPE_LEVEL_LOW) + return -EINVAL; + + if (trigger & IRQ_TYPE_LEVEL_HIGH) + intc->tango_irq_to_spi[hwirq] = LEVEL_SPI; + + if (trigger & IRQ_TYPE_EDGE_RISING) { + for (spi = 1; spi < SPI_MAX; ++spi) { + if (intc->spi_to_tango_irq[spi] == 0) { + intc->tango_irq_to_spi[hwirq] = spi; + intc->spi_to_tango_irq[spi] = hwirq; + break; + } + } + if (spi == SPI_MAX) + return -ENOSPC; + } + + irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &tango_chip, intc); + irq_set_handler(virq, handle_simple_irq); + + return 0; +} + +static struct irq_domain_ops dom_ops = { + .xlate = irq_domain_xlate_twocell, + .alloc = tango_alloc, +}; + +static int __init map_irq(struct device_node *gic, int spi, int trigger) +{ + struct of_phandle_args irq_data = { gic, 3, { 0, spi, trigger }}; + return irq_create_of_mapping(&irq_data); +} + +static int __init tango_irq_init(struct device_node *node, struct device_node *parent) +{ + int spi, virq; + struct tango_intc *intc; + + intc = kzalloc(sizeof(*intc), GFP_KERNEL); + if (!intc) + panic("%s: Failed to kalloc\n", node->name); + + virq = map_irq(parent, LEVEL_SPI, IRQ_TYPE_LEVEL_HIGH); + if (!virq) + panic("%s: Failed to map IRQ %d\n", node->name, LEVEL_SPI); + + irq_set_chained_handler_and_data(virq, tango_level_isr, intc); + + for (spi = 1; spi < SPI_MAX; ++spi) { + virq = map_irq(parent, spi, IRQ_TYPE_EDGE_RISING); + if (!virq) + panic("%s: Failed to map IRQ %d\n", node->name, spi); + + irq_set_chained_handler_and_data(virq, tango_edge_isr, intc); + } + + spin_lock_init(&intc->lock); + intc->base = of_iomap(node, 0); + intc->dom = irq_domain_add_linear(node, IRQ_MAX, &dom_ops, intc); + if (!intc->base || !intc->dom) + panic("%s: Failed to setup IRQ controller\n", node->name); + + return 0; +} +IRQCHIP_DECLARE(tango_intc, "sigma,smp8759-intc", tango_irq_init);