From patchwork Mon Jun 6 15:10:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Holger Freyther X-Patchwork-Id: 852362 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p56FBDWF007839 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 6 Jun 2011 15:11:35 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QTbSE-0005qJ-84; Mon, 06 Jun 2011 15:10:58 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QTbSD-0007MF-Qp; Mon, 06 Jun 2011 15:10:57 +0000 Received: from gandharva.secretlabs.de ([78.46.147.237]) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QTbSA-0007Lw-1O for linux-arm-kernel@lists.infradead.org; Mon, 06 Jun 2011 15:10:54 +0000 Received: from [192.168.0.101] (91-64-83-241-dynip.superkabel.de [91.64.83.241]) by gandharva.secretlabs.de (Postfix) with ESMTPA id 64EE91B10CE1; Mon, 6 Jun 2011 15:16:37 +0000 (UTC) Message-ID: <4DECEDF9.4010202@selfish.org> Date: Mon, 06 Jun 2011 17:10:49 +0200 From: Holger Freyther User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.17) Gecko/20110424 Lightning/1.0b2 Thunderbird/3.1.10 MIME-Version: 1.0 To: Thomas Gleixner Subject: Re: TI-Davinci 6446 oops on interrupts References: <4DECCADE.6080100@selfish.org> <4DECD8C0.6010908@freyther.de> In-Reply-To: X-Enigmail-Version: 1.1.1 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110606_111054_268606_967828E5 X-CRM114-Status: GOOD ( 14.50 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- Cc: Kevin Hilman , linux-arm-kernel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 06 Jun 2011 15:11:35 +0000 (UTC) On 06/06/2011 04:54 PM, Thomas Gleixner wrote: >> I resorted to printf debugging, it is IRQ 56 which is the IRQ_GPIOBNK0.. so I >> wonder if this IRQ should end up in the GC GPIO code at all? > > That depends on davinci_soc_info.intc_irq_num. > > #define DAVINCI_N_AINTC_IRQ 64 > #define DA830_N_CP_INTC_IRQ 96 > #define TNETV107X_N_CP_INTC_IRQ 96 > > No idea which one applies to your machine, but for all in tree boards > 56 is in the range of intc interrupts. It should be the DAVINCI_N_AINTC_IRQ (dm6446.c:davinci_soc_info_dm644x), I have commented out the AINTC code in davinci_gpio_irq_setup and my crash is gone, so without knowing the code at all I assume one should not end where we end up.. or at least not with the parameters. I have instrumented the GC IRQ code and I get: IRQ40: Interrupt is 40 32 RegBase is 0xfec48000 offset 28 IRQ56: Interrupt is 56... RegBase is 0x5ffffbff offset 28 and both interrupts should be on REG1.. so for IRQ56 it looks like this method is entered with bogus data. Again, I have no idea about the underlying code, but could there be an issue with chained irq and the GC IRC code? going to dig deeper.. holger diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index 31a9db7..fc505c3 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -74,6 +74,13 @@ void irq_gc_mask_set_bit(struct irq_data *d) void irq_gc_mask_clr_bit(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + + if (d->irq > 31) { + printk(KERN_ERR "Interrupt is %d %d\n", d->irq, gc->irq_base); + printk(KERN_ERR "RegBase is 0x%p offset %lu\n", gc->reg_base, + cur_regs(d)->mask); + } + u32 mask = 1 << (d->irq - gc->irq_base); irq_gc_lock(gc);