From patchwork Thu Jan 30 17:33:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 13954788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C746C0218A for ; Thu, 30 Jan 2025 17:40:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=i3QkP73j7x5d+AQphvPwjsqmp9onXYdrNTUKx9rTazk=; b=PyBtZ8HTKSve9k82KqenTvjg3D wZQLJo7KDVKBGgNki9vrbAXsR7BRZ7fUF2OR6wY0VRMx+lL7WK6dylPHVKx1843RHR5kPM7EuJjJ2 eQr4kqe/VzM4IArB7LeWF09fIQ3ww7BjFb8kNHTcFwBfZ7c2EQYF3y40A5TehIs3idfzJgVTVdoOG fxwlCmIztbOpuVzDYQi/FajHIjILFvinn6HqzJs/QFEaOKgsUC1zPfvdZpJEII3BPIY2o94p0de+L T0JeU1h+WIiO6Hm1YCi8Tam6R8bnYpuV5L1dOrDG4dae+mzX+rVW87MxELmRXntu73H8kiefroHzf NIuZqiMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tdYW5-00000009JAr-3Aqy; Thu, 30 Jan 2025 17:39:49 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tdYSD-00000009IJH-1dTA for linux-arm-kernel@lists.infradead.org; Thu, 30 Jan 2025 17:35:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258549; x=1769794549; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wan1Nd3Bl14Mogpslj9rCJupKOyLIC//emvKCJOzmww=; b=CrVbn6B+qMvg716e0uQz68GeHeI3whrF1tmNHM2Q9/Q1wD4YKWAazuih UAqeFES1IYlTke5Vl+xjOqqQ3Jjm8AO14rrZhgbiT+MX0rkPRvQCZUTY0 0UZKXOpEWMARDVeYdFFK8kl/qtrNIrVXsPAk3dMEKdYfyLejOR1PHGdum JslBp7Q4St1U0HrtUiJorWppzHaD3DZnP0MxnolkM+NKOcXpZTD73t7Xd l3m6D6e1zx0HHl68O1AZj7xBJwrR3Z8wyknF6pGRrGpmUWPDXi4IowtT0 g/y88aFZ6whs4REXWQ1WA4jsqxG51T8b9Y5SFrV7aL/CjGHMemIzXL3ZC w==; X-CSE-ConnectionGUID: X8noN3xrSZmPEckyVo5bzw== X-CSE-MsgGUID: UJXhY5GLRvWt9YKMkDMqRA== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="204622974" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:35:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:42 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:42 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 15/16] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support Date: Thu, 30 Jan 2025 10:33:55 -0700 Message-ID: <4c7226eb6e70ebd8fcc3e1afd0dbdf3d5a16f2a6.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250130_093549_491307_0EEA625B X-CRM114-Status: GOOD ( 10.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ryan Wanner Add support for reset controller, wake up alarm timers, and shutdown controller. Add SRAM, SFR, secumod, UDDRC, and DDR3phy to enable support for low power modes. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 77 +++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 854b30d15dcd4..8e117586e5902 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -46,12 +46,42 @@ slow_xtal: clock-slowxtal { }; }; + ns_sram: sram@100000 { + compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100000 0x20000>; + ranges; + }; + soc { compatible = "simple-bus"; ranges; #address-cells = <1>; #size-cells = <1>; + securam: sram@e0000800 { + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000800 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe0000800 0x4000>; + no-memory-wc; + }; + + secumod: secumod@e0004000 { + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + + sfrbu: sfr@e0008000 { + compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; + reg = <0xe0008000 0x20>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -76,6 +106,31 @@ pmc: clock-controller@e0018000 { clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d100 { + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + + shdwc: poweroff@e001d200 { + compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; + reg = <0xe001d200 0x20>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtc@e001d300 { + compatible = "microchip,sama7d65-rtt", "microchip,sama7g5-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d300 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -83,6 +138,18 @@ clk32k: clock-controller@e001d500 { #clock-cells = <1>; }; + gpbr: gpbr@e001d700 { + compatible = "microchip,sama7d65-gpbr", "syscon"; + reg = <0xe001d700 0x48>; + }; + + rtc: rtc@e001d800 { + compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; + reg = <0xe001d800 0x30>; + interrupts = ; + clocks = <&clk32k 1>; + }; + sdmmc1: mmc@e1208000 { compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; reg = <0xe1208000 0x400>; @@ -132,6 +199,16 @@ uart6: serial@200 { }; }; + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>,