From patchwork Thu Nov 8 16:55:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 1716581 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 4707E3FCDE for ; Thu, 8 Nov 2012 16:56:59 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWVNj-0003aA-T9; Thu, 08 Nov 2012 16:55:07 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TWVNf-0003ZN-I4 for linux-arm-kernel@lists.infradead.org; Thu, 08 Nov 2012 16:55:04 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id qA8Gt1E2031741; Thu, 8 Nov 2012 10:55:01 -0600 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA8Gt1eO029292; Thu, 8 Nov 2012 10:55:01 -0600 Received: from [192.157.144.139] (192.157.144.139) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Thu, 8 Nov 2012 10:55:00 -0600 Message-ID: <509BE3E4.8050008@ti.com> Date: Thu, 8 Nov 2012 10:55:00 -0600 From: Jon Hunter User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121028 Thunderbird/16.0.2 MIME-Version: 1.0 To: Santosh Shilimkar Subject: Re: [PATCH V2 03/14] ARM: OMAP3+: Implement timer workaround for errata i103 and i767 References: <1352314890-22224-1-git-send-email-jon-hunter@ti.com> <1352314890-22224-4-git-send-email-jon-hunter@ti.com> <509ADD28.20707@ti.com> <509AEEA4.80804@ti.com> <509AF21C.7020105@ti.com> In-Reply-To: <509AF21C.7020105@ti.com> X-Originating-IP: [192.157.144.139] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121108_115503_898805_FA94DFE7 X-CRM114-Status: GOOD ( 36.93 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.41 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Tony Lindgren , Kevin Hilman , Paul Walmsley , linux-omap , linux-arm X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On 11/07/2012 05:43 PM, Santosh Shilimkar wrote: > On Wednesday 07 November 2012 05:28 PM, Jon Hunter wrote: >> >> On 11/07/2012 04:14 PM, Santosh Shilimkar wrote: >> >>> Looks sensible considering alternative WAs. >>> >>> Acked-by: Santosh Shilimkar >> >> Thanks. With further thought I think that it would be best to combine >> patches #2 and #3. Really the main motivation here is the errata >> workaround and without actually benchmarking the timer read I should >> not claim the improvement in overhead as stated in patch #2. So I >> have combined #2 and #3 and updated the changelog/comments >> appropriately. Let me know if you guys are ok with this. >> > Yep. Sounds good. Updated, removing the additional OMAP_CLKEVT/SRC_POSTEDMODE definitions. Cheers Jon From 5b55c6c2ca6f41e37f531d8ca0ea80a0e49f3e4d Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 27 Sep 2012 12:47:43 -0500 Subject: [PATCH 2/2] ARM: OMAP3+: Implement timer workaround for errata i103 and i767 Errata Titles: i103: Delay needed to read some GP timer, WD timer and sync timer registers after wakeup (OMAP3/4) i767: Delay needed to read some GP timer registers after wakeup (OMAP5) Description (i103/i767): If a General Purpose Timer (GPTimer) is in posted mode (TSICR [2].POSTED=1), due to internal resynchronizations, values read in TCRR, TCAR1 and TCAR2 registers right after the timer interface clock (L4) goes from stopped to active may not return the expected values. The most common event leading to this situation occurs upon wake up from idle. GPTimer non-posted synchronization mode is not impacted by this limitation. Workarounds: 1). Disable posted mode 2). Use static dependency between timer clock domain and MPUSS clock domain 3). Use no-idle mode when the timer is active Workarounds #2 and #3 are not pratical from a power standpoint and so workaround #1 has been implemented. Disabling posted mode adds some CPU overhead for configuring and reading the timers as the CPU has to wait for accesses to be re-synchronised within the timer. However, disabling posted mode guarantees correct operation. Please note that it is safe to use posted mode for timers if the counter (TCRR) and capture (TCARx) registers will never be read. An example of this is the clock-event system timer. This is used by the kernel to schedule events however, the timers counter is never read and capture registers are not used. Given that the kernel configures this timer often yet never reads the counter register it is safe to enable posted mode in this case. Hence, for the timer used for kernel clock-events, posted mode is enabled by overriding the errata for devices that are impacted by this defect. For drivers using the timers that do not read the counter or capture registers and wish to use posted mode, can override the errata and enable posted mode by making the following function calls. omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767); omap_dm_timer_enable_posted(timer); Both dmtimers and watchdogs are impacted by this defect this patch only implements the workaround for the dmtimer. Currently the watchdog driver does not read the counter register and so no workaround is necessary. Posted mode will be disabled for all OMAP2+ devices (including AM33xx) using a GP timer as a clock-source timer to guarantee correct operation. This is not necessary for OMAP24xx devices but the default clock-source timer for OMAP24xx devices is the 32k-sync timer and not the GP timer and so should not have any impact. This should be re-visited for future devices if this errata is fixed. Confirmed with Vaibhav Hiremath that this bug also impacts AM33xx devices. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 35 +++++++++++++---- arch/arm/plat-omap/dmtimer.c | 59 ++++++++++++++++++++++++++++- arch/arm/plat-omap/include/plat/dmtimer.h | 19 ++++++++-- 3 files changed, 100 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index ad427ba..e99b95c 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -224,7 +224,8 @@ void __init omap_dmtimer_init(void) static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, int gptimer_id, const char *fck_source, - const char *property) + const char *property, + int posted) { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ const char *oh_name; @@ -310,10 +311,15 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, } __omap_dm_timer_init_regs(timer); __omap_dm_timer_reset(timer, 1, 1); - timer->posted = 1; - timer->rate = clk_get_rate(timer->fclk); + if (posted) + omap_dm_timer_enable_posted(timer); + /* Check that the intended posted configuration matches the actual */ + if (posted != timer->posted) + return -EINVAL; + + timer->rate = clk_get_rate(timer->fclk); timer->reserved = 1; return res; @@ -325,7 +331,17 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, { int res; - res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property); + omap_dm_timer_populate_errata(&clkev); + + /* + * For clock-event timers we never read the timer counter and + * so we are not impacted by errata i103 and i767. Therefore, + * we can safely ignore this errata for clock-event timers. + */ + omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); + + res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, + OMAP_TIMER_POSTED); BUG_ON(res); omap2_gp_timer_irq.dev_id = &clkev; @@ -359,7 +375,7 @@ static bool use_gptimer_clksrc; static cycle_t clocksource_read_cycles(struct clocksource *cs) { return (cycle_t)__omap_dm_timer_read_counter(&clksrc, - OMAP_TIMER_POSTED); + OMAP_TIMER_NONPOSTED); } static struct clocksource clocksource_gpt = { @@ -374,7 +390,7 @@ static u32 notrace dmtimer_read_sched_clock(void) { if (clksrc.reserved) return __omap_dm_timer_read_counter(&clksrc, - OMAP_TIMER_POSTED); + OMAP_TIMER_NONPOSTED); return 0; } @@ -452,12 +468,15 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, { int res; - res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL); + omap_dm_timer_populate_errata(&clksrc); + + res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL, + OMAP_TIMER_NONPOSTED); BUG_ON(res); __omap_dm_timer_load_start(&clksrc, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, - OMAP_TIMER_POSTED); + OMAP_TIMER_NONPOSTED); setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index b09e556..4abbbe5 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -131,8 +131,8 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer) } __omap_dm_timer_reset(timer, 0, 0); + omap_dm_timer_enable_posted(timer); omap_dm_timer_disable(timer); - timer->posted = 1; } int omap_dm_timer_prepare(struct omap_dm_timer *timer) @@ -176,6 +176,61 @@ int omap_dm_timer_reserve_systimer(int id) return 0; } +/** + * omap_dm_timer_populate_errata - populate errata flags for a timer + * @timer: pointer to timer handle + * + * For a given timer, populate the timer errata flags that are specific to the + * OMAP device being used. + */ +void omap_dm_timer_populate_errata(struct omap_dm_timer *timer) +{ + timer->errata = 0; + + if (cpu_class_is_omap1() || cpu_is_omap24xx()) + return; + + timer->errata = OMAP_TIMER_ERRATA_I103_I767; +} + +/** + * omap_dm_timer_override_errata - override errata flags for a timer + * @timer: pointer to timer handle + * @errata: errata flags to be ignored + * + * For a given timer, override a timer errata by clearing the flags specified + * by the errata argument. A specific erratum should only be overridden for a + * timer if the timer is used in such a way the erratum has no impact. + */ +void omap_dm_timer_override_errata(struct omap_dm_timer *timer, u32 errata) +{ + timer->errata &= ~errata; +} + +/* + * omap_dm_timer_enable_posted - enables write posted mode + * @timer: pointer to timer instance handle + * + * Enables the write posted mode for the timer. When posted mode is enabled + * writes to certain timer registers are immediately acknowledged by the + * internal bus and hence prevents stalling the CPU waiting for the write to + * complete. Enabling this feature can improve performance for writing to the + * timer registers. + */ +void omap_dm_timer_enable_posted(struct omap_dm_timer *timer) +{ + if (timer->posted) + return; + + if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) + return; + + omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, + OMAP_TIMER_CTRL_POSTED); + timer->context.tsicr = OMAP_TIMER_CTRL_POSTED; + timer->posted = OMAP_TIMER_POSTED; +} + struct omap_dm_timer *omap_dm_timer_request(void) { struct omap_dm_timer *timer = NULL, *t; @@ -803,6 +858,8 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) timer->irq = irq->start; timer->pdev = pdev; + omap_dm_timer_populate_errata(timer); + /* Skip pm_runtime_enable for OMAP1 */ if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { pm_runtime_enable(dev); diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 835c3bdf..ef93017 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -36,6 +36,7 @@ #include #include #include +#include #ifndef __ASM_ARCH_DMTIMER_H #define __ASM_ARCH_DMTIMER_H @@ -66,6 +67,16 @@ #define OMAP_TIMER_NEEDS_RESET 0x10000000 #define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 +/* + * timer errata flags + * + * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This + * errata prevents us from using posted mode on these devices, unless the + * timer counter register is never read. For more details please refer to + * the OMAP3/4/5 errata documents. + */ +#define OMAP_TIMER_ERRATA_I103_I767 0x80000000 + struct omap_timer_capability_dev_attr { u32 timer_capability; }; @@ -101,6 +112,9 @@ struct dmtimer_platform_data { }; int omap_dm_timer_reserve_systimer(int id); +void omap_dm_timer_populate_errata(struct omap_dm_timer *timer); +void omap_dm_timer_override_errata(struct omap_dm_timer *timer, u32 errata); +void omap_dm_timer_enable_posted(struct omap_dm_timer *timer); struct omap_dm_timer *omap_dm_timer_request(void); struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap); @@ -271,6 +285,7 @@ struct omap_dm_timer { int ctx_loss_count; int revision; u32 capability; + u32 errata; struct platform_device *pdev; struct list_head node; }; @@ -342,10 +357,6 @@ static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer, l |= 1 << 2; __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); - - /* Match hardware reset default of posted mode */ - __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, - OMAP_TIMER_CTRL_POSTED, 0); } static inline int __omap_dm_timer_set_source(struct clk *timer_fck,