From patchwork Wed Dec 19 20:54:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 1897151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 5A2393FC81 for ; Wed, 19 Dec 2012 20:57:17 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TlQf9-0000cm-87; Wed, 19 Dec 2012 20:54:47 +0000 Received: from wolverine02.qualcomm.com ([199.106.114.251]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TlQf5-0000bo-LK for linux-arm-kernel@lists.infradead.org; Wed, 19 Dec 2012 20:54:44 +0000 X-IronPort-AV: E=Sophos;i="4.84,318,1355126400"; d="scan'208";a="15371563" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 19 Dec 2012 12:54:40 -0800 Received: from [10.46.166.8] (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 0E49910004B4; Wed, 19 Dec 2012 12:54:39 -0800 (PST) Message-ID: <50D2298F.2030308@codeaurora.org> Date: Wed, 19 Dec 2012 12:54:39 -0800 From: Stephen Boyd User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Soren Brinkmann Subject: Re: [PATCH 4/4] clk: zynq: Use of_init_clk_data() References: <1355778135-32458-1-git-send-email-sboyd@codeaurora.org> <1355778135-32458-5-git-send-email-sboyd@codeaurora.org> <50D223DD.8070208@codeaurora.org> In-Reply-To: <50D223DD.8070208@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121219_155444_011940_6A29E3B0 X-CRM114-Status: GOOD ( 23.90 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.251 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Josh Cartwright , Mike Turquette , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On 12/19/12 12:30, Stephen Boyd wrote: > On 12/19/12 11:22, Soren Brinkmann wrote: >> Hi Stephen, >> >> I guess Josh is the better person to talk about this, since he created the >> patches regarding common clock for mainline, but I tried running your series >> and ran into this: >> >> Unable to handle kernel NULL pointer dereference at virtual address 0000002a >> pgd = c0004000 >> [0000002a] *pgd=00000000 >> Internal error: Oops: 5 [#1] PREEMPT ARM >> Modules linked in: >> CPU: 0 Tainted: G W (3.7.0-rc3-00025-gc11ffdd-dirty #246) >> PC is at __clk_prepare+0x20/0x80 >> LR is at clk_prepare+0x2c/0x44 >> pc : [] lr : [] psr: a0000153 >> sp : ee02fdd0 ip : ee02fde8 fp : ee02fde4 >> r10: 00000000 r9 : 00000000 r8 : c0587884 >> r7 : 00000000 r6 : c05aab98 r5 : fffffffe r4 : fffffffe >> r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : fffffffe >> Flags: NzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment kernel >> Control: 18c5387d Table: 00004059 DAC: 00000015 >> Process swapper (pid: 1, stack limit = 0xee02e230) >> Stack: (0xee02fdd0 to 0xee030000) >> fdc0: c05b6a18 fffffffe ee02fdfc ee02fde8 >> fde0: c0316628 c0316588 ee085400 fffffffe ee02fe24 ee02fe00 c03c1358 c0316608 >> fe00: c03c1328 ee085410 c05aab98 c05aab98 00000000 c0587884 ee02fe34 ee02fe28 >> fe20: c026a5c0 c03c1334 ee02fe5c ee02fe38 c0268f50 c026a5a8 c026a7b8 c0313ac0 >> fe40: ee085410 ee085410 ee085444 c05aab98 ee02fe7c ee02fe60 c02691c0 c0268e18 >> fe60: c0269150 c05aab98 c0269150 00000000 ee02fea4 ee02fe80 c0267320 c026915c >> fe80: ee00948c ee096df0 c021e02c c05aab98 ed9a0bc0 c05ab3a8 ee02feb4 ee02fea8 >> fea0: c0268a28 c02672d0 ee02fee4 ee02feb8 c0268408 c0268a0c c04b56d1 00000000 >> fec0: ee02fee4 c05aab98 c0565e60 00000000 0000006f c0587884 ee02ff14 ee02fee8 >> fee0: c0269990 c0268340 00000000 00000000 c0565e60 00000000 0000006f c0587884 >> ff00: 00000000 00000000 ee02ff24 ee02ff18 c026a9cc c02698f0 ee02ff3c ee02ff28 >> ff20: c0565e84 c026a984 ee02e000 ee02ff40 ee02ff74 ee02ff40 c00086f8 c0565e6c >> ff40: c04f72e4 00000000 ee02ff74 00000006 00000006 c0571dac c0571d8c 0000006f >> ff60: c0587884 00000000 ee02ffac ee02ff78 c03bf9c4 c0008664 00000006 00000006 >> ff80: c05511a8 00000000 ee02ffac 00000000 c03bf8cc 00000000 00000000 00000000 >> ffa0: 00000000 ee02ffb0 c000ea98 c03bf8d8 00000000 00000000 00000000 00000000 >> ffc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 >> ffe0: 00000000 00000000 00000000 00000000 00000013 00000000 0158ec21 0eced1ff >> [] (__clk_prepare+0x20/0x80) from [] (clk_prepare+0x2c/0x44) >> [] (clk_prepare+0x2c/0x44) from [] (xuartps_probe+0x30/0x1ac >> ) >> [] (xuartps_probe+0x30/0x1ac) from [] (platform_drv_probe+0x >> 24/0x28) >> [] (platform_drv_probe+0x24/0x28) from [] (driver_probe_devi >> ce+0x144/0x344) >> [] (driver_probe_device+0x144/0x344) from [] (__driver_attac >> h+0x70/0x94) >> [] (__driver_attach+0x70/0x94) from [] (bus_for_each_dev+0x5 >> c/0x8c) >> [] (bus_for_each_dev+0x5c/0x8c) from [] (driver_attach+0x28/ >> 0x30) >> [] (driver_attach+0x28/0x30) from [] (bus_add_driver+0xd4/0x >> 254) >> [] (bus_add_driver+0xd4/0x254) from [] (driver_register+0xac >> /0x14c) >> [] (driver_register+0xac/0x14c) from [] (platform_driver_reg >> ister+0x54/0x68) >> [] (platform_driver_register+0x54/0x68) from [] (xuartps_ini >> t+0x24/0x44) >> [] (xuartps_init+0x24/0x44) from [] (do_one_initcall+0xa0/0x >> 170) >> [] (do_one_initcall+0xa0/0x170) from [] (kernel_init+0xf8/0x >> 2ac) >> [] (kernel_init+0xf8/0x2ac) from [] (ret_from_fork+0x14/0x20 >> ) >> Code: e8bd4000 e2504000 01a05004 0a000015 (e594302c) >> ---[ end trace 1b75b31a2719ed1d ]--- >> Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b >> >> >> A probably unique thing I do is, I set the status of uart0 to disabled. This way >> I can reuse my rootfs which does not run getty on ttyPS1. And this worked fine >> before. >> > Thanks for testing. It seems that clocks are failing to register. Please > try this patch. > Also, why are clock-names an optional property in devicetree? It would be nice to not have two different APIs for consumers (i.e. drivers) to get clocks from devicetree bindings. I suggest we do this for your uart driver so that you can use the regular clock APIs and not the of_* ones. We should get rid of of_clk_get(). ---->8----- diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 5914b56..eef5f0c 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -45,6 +45,7 @@ reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; clocks = <&uart_clk 0>; + clock-names = "ref"; }; uart1: uart@e0001000 { @@ -52,6 +53,7 @@ reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; clocks = <&uart_clk 1>; + clock-names = "ref"; }; slcr: slcr@f8000000 { diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c index 2be22a2..6868e6b 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -947,10 +947,10 @@ static int xuartps_probe(struct platform_device *pdev) struct resource *res, *res2; struct clk *clk; - clk = of_clk_get(pdev->dev.of_node, 0); - if (!clk) { - dev_err(&pdev->dev, "no clock specified\n"); - return -ENODEV; + clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "failed to get clock\n"); + return PTR_ERR(clk); } rc = clk_prepare_enable(clk);