From patchwork Thu May 2 19:54:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Hentschel?= X-Patchwork-Id: 2513611 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 786163FCA5 for ; Thu, 2 May 2013 19:56:41 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UXzbe-00057B-AC; Thu, 02 May 2013 19:55:54 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UXzb4-0000pY-4S; Thu, 02 May 2013 19:55:18 +0000 Received: from moutng.kundenserver.de ([212.227.17.9]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UXzb1-0000ot-1C for linux-arm-kernel@lists.infradead.org; Thu, 02 May 2013 19:55:16 +0000 Received: from [192.168.178.50] (pD95340FD.dip0.t-ipconnect.de [217.83.64.253]) by mrelayeu.kundenserver.de (node=mreu3) with ESMTP (Nemesis) id 0Lx0lJ-1UVvFi0qTZ-016hgU; Thu, 02 May 2013 21:54:44 +0200 Message-ID: <5182C480.3080001@dawncrow.de> Date: Thu, 02 May 2013 21:54:40 +0200 From: =?ISO-8859-1?Q?Andr=E9_Hentschel?= User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130329 Thunderbird/17.0.5 MIME-Version: 1.0 To: Will Deacon Subject: Re: [PATCHv2] arm: Preserve TPIDRURW on context switch References: <517168BB.3070903@dawncrow.de> <20130422143616.GP14496@n2100.arm.linux.org.uk> <20130422151836.GA15665@mudshark.cambridge.arm.com> <5175A697.3080308@dawncrow.de> <20130423091536.GB17593@mudshark.cambridge.arm.com> <51770E4E.2040003@dawncrow.de> <20130424094251.GA21850@mudshark.cambridge.arm.com> In-Reply-To: <20130424094251.GA21850@mudshark.cambridge.arm.com> X-Provags-ID: V02:K0:gewfY/gK1oy8cLsLdpC37h+AK+bjd8bOYMDFVwSbAJM pu3npKXPZx2xpyzWXOK5XzC/65Ukf3m1k3GgW7EyOncFws3Def Ysj0QspgngqDhRikr5rG5wqIMRZDcfmBm8ib3n5GM89C4z91Fv 6+A9f2Sn3nAJe0QAa/EVMnT83q04sF9Cw3lDrU4d77UMLbQ9m1 2Dbxdy8e8PLDEg/4Nn2RlMlTylCGx5wpZFG2s524iesL+p3CXj +i2PTTgk8/KPTW7qWEtPYis9kn3uE62h9w7w9IkSNJ2+q4FHKC oS0IX8b4ri/brdVeXGABQs87PfACiC1Owwcuv6CYn9nUUmmeup GvZQxIxPkEXYP2wx1dbM= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130502_155515_286892_8FBDCF33 X-CRM114-Status: GOOD ( 16.75 ) X-Spam-Score: 0.6 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.227.17.9 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 2.5 SUSPICIOUS_RECIPS Similar addresses in recipient list -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "linux-arch@vger.kernel.org" , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Am 24.04.2013 11:42, schrieb Will Deacon: > Hi Andrew, > > On Tue, Apr 23, 2013 at 11:42:22PM +0100, André Hentschel wrote: >> Am 23.04.2013 11:15, schrieb Will Deacon: >>> You could introduce `get' tls functions, which don't do anything for CPUs >>> without the relevant registers. >> >> Before i have another round of testing and patch formatting/sending, >> what about the untested patch below? > > Ok. Comments inline. I answered to that seperatly. Here is another try based on your comments: diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index cddda1f..bb5b48d 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -58,7 +58,7 @@ struct thread_info { struct cpu_context_save cpu_context; /* cpu context */ __u32 syscall; /* syscall number */ __u8 used_cp[16]; /* thread used copro */ - unsigned long tp_value; + unsigned long tp_value[2]; #ifdef CONFIG_CRUNCH struct crunch_state crunchstate; #endif diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index 73409e6..02f8674 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -2,48 +2,87 @@ #define __ASMARM_TLS_H #ifdef __ASSEMBLY__ + .macro check_hwcap_tls, tmp1 + ldr \tmp1, =elf_hwcap + ldr \tmp1, [\tmp1, #0] + tst \tmp1, #HWCAP_TLS @ hardware TLS available? + .endm + + + .macro get_tls_none, tp, tmp1 + .endm + + .macro get_tls_v6k, tp, tmp1 + mrc p15, 0, \tmp1, c13, c0, 2 @ get user r/w TLS register + str \tmp1, [\tp, #4] + .endm + + .macro get_tls_v6, tp, tmp1 + check_hwcap_tls \tmp1 + mrcne p15, 0, \tmp1, c13, c0, 2 @ get user r/w TLS register + strne \tmp1, [\tp, #4] + .endm + + .macro set_tls_none, tp, tmp1, tmp2 .endm .macro set_tls_v6k, tp, tmp1, tmp2 - mcr p15, 0, \tp, c13, c0, 3 @ set TLS register - mov \tmp1, #0 - mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register + ldrd \tmp1, \tmp2, [\tp] + mcr p15, 0, \tmp1, c13, c0, 3 @ set user r/o TLS register + mcr p15, 0, \tmp2, c13, c0, 2 @ set user r/w TLS register .endm .macro set_tls_v6, tp, tmp1, tmp2 - ldr \tmp1, =elf_hwcap - ldr \tmp1, [\tmp1, #0] mov \tmp2, #0xffff0fff - tst \tmp1, #HWCAP_TLS @ hardware TLS available? - mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register - movne \tmp1, #0 - mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register - streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 + check_hwcap_tls \tmp1 + ldrdne \tmp1, \tmp2, [\tp] + ldreq \tmp1, [\tp] + mcrne p15, 0, \tmp1, c13, c0, 3 @ yes, set user r/o TLS register + mcrne p15, 0, \tmp2, c13, c0, 2 @ set user r/w TLS register + streq \tmp1, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 .endm .macro set_tls_software, tp, tmp1, tmp2 - mov \tmp1, #0xffff0fff - str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0 + ldr \tmp1, [\tp] + mov \tmp2, #0xffff0fff + str \tmp1, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 .endm #endif #ifdef CONFIG_TLS_REG_EMUL #define tls_emu 1 #define has_tls_reg 1 +#define get_tls get_tls_none #define set_tls set_tls_none #elif defined(CONFIG_CPU_V6) #define tls_emu 0 #define has_tls_reg (elf_hwcap & HWCAP_TLS) +#define get_tls get_tls_v6 #define set_tls set_tls_v6 #elif defined(CONFIG_CPU_32v6K) #define tls_emu 0 #define has_tls_reg 1 +#define get_tls get_tls_v6k #define set_tls set_tls_v6k #else #define tls_emu 0 #define has_tls_reg 0 +#define get_tls get_tls_none #define set_tls set_tls_software #endif +#ifndef __ASSEMBLY__ +static inline void get_tpidrurw(unsigned long *tpidrurw) +{ + unsigned long t; +#ifdef CONFIG_TLS_REG_EMUL + return; +#endif + if (!has_tls_reg) return; + __asm__("mcr p15, 0, %0, c13, c0, 2" : : "r" (t)); + *tpidrurw = t; +} +#endif + #endif /* __ASMARM_TLS_H */ diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 0f82098..2c892b2 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -728,7 +728,7 @@ ENTRY(__switch_to) UNWIND(.fnstart ) UNWIND(.cantunwind ) add ip, r1, #TI_CPU_SAVE - ldr r3, [r2, #TI_TP_VALUE] + add r3, r1, #TI_TP_VALUE ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack THUMB( str sp, [ip], #4 ) @@ -736,6 +736,8 @@ ENTRY(__switch_to) #ifdef CONFIG_CPU_USE_DOMAINS ldr r6, [r2, #TI_CPU_DOMAIN] #endif + get_tls r3, r4 + add r3, r2, #TI_TP_VALUE set_tls r3, r4, r5 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) ldr r7, [r2, #TI_TASK] diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 047d3e4..a13bbc8 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -395,7 +396,10 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start, clear_ptrace_hw_breakpoint(p); if (clone_flags & CLONE_SETTLS) - thread->tp_value = childregs->ARM_r3; + { + thread->tp_value[0] = childregs->ARM_r3; + get_tpidrurw(&thread->tp_value[1]); + } thread_notify(THREAD_NOTIFY_COPY, thread); diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 03deeff..2bc1514 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request, #endif case PTRACE_GET_THREAD_AREA: - ret = put_user(task_thread_info(child)->tp_value, + ret = put_user(task_thread_info(child)->tp_value[0], datap); break; diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 1c08911..f9d6259 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -588,7 +588,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) return regs->ARM_r0; case NR(set_tls): - thread->tp_value = regs->ARM_r0; + thread->tp_value[0] = regs->ARM_r0; if (tls_emu) return 0; if (has_tls_reg) { @@ -706,7 +706,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr) int reg = (instr >> 12) & 15; if (reg == 15) return 1; - regs->uregs[reg] = current_thread_info()->tp_value; + regs->uregs[reg] = current_thread_info()->tp_value[0]; regs->ARM_pc += 4; return 0; }