From patchwork Mon Jul 15 17:14:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Hentschel?= X-Patchwork-Id: 2827681 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 93514C0AB2 for ; Mon, 15 Jul 2013 17:15:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6ACD420213 for ; Mon, 15 Jul 2013 17:15:42 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4797D2020E for ; Mon, 15 Jul 2013 17:15:41 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UymN7-0001j4-Ht; Mon, 15 Jul 2013 17:15:37 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UymN4-0003Ll-PO; Mon, 15 Jul 2013 17:15:34 +0000 Received: from moutng.kundenserver.de ([212.227.126.187]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UymN1-0003LE-GZ for linux-arm-kernel@lists.infradead.org; Mon, 15 Jul 2013 17:15:32 +0000 Received: from [192.168.178.50] (pD9532696.dip0.t-ipconnect.de [217.83.38.150]) by mrelayeu.kundenserver.de (node=mrbap4) with ESMTP (Nemesis) id 0MCID3-1UqDn11i65-009naX; Mon, 15 Jul 2013 19:14:59 +0200 Message-ID: <51E42E11.1010903@dawncrow.de> Date: Mon, 15 Jul 2013 19:14:57 +0200 From: =?ISO-8859-1?Q?Andr=E9_Hentschel?= User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130623 Thunderbird/17.0.7 MIME-Version: 1.0 To: "linux-arch@vger.kernel.org" Subject: arm: Only load TLS values when needed X-Provags-ID: V02:K0:GQloeYutGTjxLAPN8WrDjKtLuI98j8EbR/yS8domUlH 4vhtD1d+n+3EJ9IPU8e5nLjRdUpLA78ThzD4Q5PTj3pE28RkFM pbn868Q1EVGItoqaO3qU17kvsehjm2RjVJQ0vuGoVh3JykxwTe yt7lXXb+uM/ZsNRl1ToC5uzX2Q9kRKPNjs7B/MJU8pnHdRlH0I fYOvOIJeiuwM6ELsz/f7ksRPi5pf6GWGHP361xkLirC17EI+Yv 1U4DVQHY1R6VfDX/sSDbblgggeVbBzI7h/HP+0N5Rsirh40Idb Cndvj3NwY3d3i5am07K8SDGwP9HCHt0hzV71V6uUnycSPy8Ir5 dPhiryKASBNy1ltqVjTA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130715_131531_772942_7D6B9B74 X-CRM114-Status: UNSURE ( 8.85 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) Cc: Will Deacon , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Jonathan Austin X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: André Hentschel This patch intents to reduce loading instructions when the resulting value is not used. It's a follow up on a4780adeefd042482f624f5e0d577bf9cdcbb760 Signed-off-by: André Hentschel --- This patch is against Linux 3.11-rc1 (ad81f0545ef01ea651886dddac4bef6cec930092) Thanks to everyone who helped me with a4780adeefd042482f624f5e0d577bf9cdcbb760 diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index 83259b8..3742722 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -3,29 +3,32 @@ #ifdef __ASSEMBLY__ #include - .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2 + .macro switch_tls_none, prev, next, tp, tpuser, tmp1, tmp2 .endm - .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2 + .macro switch_tls_v6k, prev, next, tp, tpuser, tmp1, tmp2 + ldrd \tp, \tpuser, [\next, #TI_TP_VALUE] @ get the next TLS and user r/w register mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register mcr p15, 0, \tp, c13, c0, 3 @ set TLS register mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register - str \tmp2, [\base, #TI_TP_VALUE + 4] @ save it + str \tmp2, [\prev, #TI_TP_VALUE + 4] @ save it .endm - .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2 + .macro switch_tls_v6, prev, next, tp, tpuser, tmp1, tmp2 ldr \tmp1, =elf_hwcap ldr \tmp1, [\tmp1, #0] mov \tmp2, #0xffff0fff + ldr \tp, [\next, #TI_TP_VALUE] @ get the next TLS register tst \tmp1, #HWCAP_TLS @ hardware TLS available? streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 - mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register + mrcne p15, 0, \tmp2, c13, c0, 2 @ get the previous user r/w register + ldrne \tpuser, [\next, #TI_TP_VALUE + 4] @ get the next user r/w register mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register - strne \tmp2, [\base, #TI_TP_VALUE + 4] @ save it + strne \tmp2, [\prev, #TI_TP_VALUE + 4] @ save it .endm - .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2 + .macro switch_tls_software, prev, next, tp, tpuser, tmp1, tmp2 mov \tmp1, #0xffff0fff str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0 .endm diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index a39cfc2a1..1484b59 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -689,12 +689,10 @@ ENTRY(__switch_to) THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack THUMB( str sp, [ip], #4 ) THUMB( str lr, [ip], #4 ) - ldr r4, [r2, #TI_TP_VALUE] - ldr r5, [r2, #TI_TP_VALUE + 4] #ifdef CONFIG_CPU_USE_DOMAINS ldr r6, [r2, #TI_CPU_DOMAIN] #endif - switch_tls r1, r4, r5, r3, r7 + switch_tls r1, r2, r4, r5, r3, r7 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) ldr r7, [r2, #TI_TASK] ldr r8, =__stack_chk_guard