From patchwork Mon Feb 3 16:43:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 3569901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 51B7F9F2E9 for ; Mon, 3 Feb 2014 16:44:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6EE2F20179 for ; Mon, 3 Feb 2014 16:44:06 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B86A20123 for ; Mon, 3 Feb 2014 16:44:05 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAMco-00023N-OF; Mon, 03 Feb 2014 16:43:58 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAMcm-0000s7-3J; Mon, 03 Feb 2014 16:43:56 +0000 Received: from eu1sys200aog106.obsmtp.com ([207.126.144.121]) by merlin.infradead.org with smtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAMcj-0000rD-2U for linux-arm-kernel@lists.infradead.org; Mon, 03 Feb 2014 16:43:53 +0000 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob106.postini.com ([207.126.147.11]) with SMTP ID DSNKUu/HMEw2V12lQsFrSBrpUMON2VbCV94B@postini.com; Mon, 03 Feb 2014 16:43:52 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 71C3AB6; Mon, 3 Feb 2014 16:42:36 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 580802CE1E; Mon, 3 Feb 2014 16:43:23 +0000 (GMT) Received: from [10.201.23.81] (10.201.23.81) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.123.3; Mon, 3 Feb 2014 17:43:25 +0100 Message-ID: <52EFC72A.6060608@st.com> Date: Mon, 3 Feb 2014 17:43:22 +0100 From: Fabrice Gasnier User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.1 MIME-Version: 1.0 To: Russell King - ARM Linux Subject: Re: Why are imprecise external aborts masked on recent kernel while booting ? References: <52EBC86D.1010509@st.com> <20140131170827.GH15937@n2100.arm.linux.org.uk> <52EF5D8E.4050600@st.com> In-Reply-To: <52EF5D8E.4050600@st.com> X-Originating-IP: [10.201.23.81] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140203_114353_318914_37075AC8 X-CRM114-Status: GOOD ( 23.94 ) X-Spam-Score: -4.2 (----) Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, I had no success with msr instruction to set CPSR.A bit. I re-checked on a 3.4 kernel, msr instruction present in former "kernel_thread_helper()" routine was not responsible for clearing CPSR.A bit. 'A' bit was cleared because SPSR was altered before executing following instruction in arch/arm/kernel/entry-header.S : movs pc, lr @ return & move spsr_svc into cpsr Sorry for the confusion in my first email: that movs instruction was responsible for clearing 'A' bit on 3.4 kernel. But on recent kernel, "restore_user_regs" macro seems no longer called for a kernel thread. So, I tried the 'cps'instruction that does it! I re-worked slightly your previous patch. I also noticed that secondary needs to be set separately. Please, could you comment on the following patch ? (I can resend correctly formated patch if you wish) : Thanks, BR, Fabrice On 02/03/2014 10:12 AM, Fabrice Gasnier wrote: > Hi Russell, > > Thank you for your help. > I just tried following patch on both 3.10 and above vanilla 3.13.1. > Unfortunately, these instructions have no effect on the arm cpsr. > I dumped regs right after msr instruction have been executed. It > remains untouched : > > Here is assembly from gdb: > > 0xc064a400 <+128>: mov r3, #256 ; 0x100 > 0xc064a404 <+132>: mrs r2, CPSR > 0xc064a408 <+136>: bic r2, r2, r3 > 0xc064a40c <+140>: msr CPSR_c, r2 > > CPSR.A bit is still set after these instructions : 0x600001d3 > Although, I see it has been cleared in r2: 0x600000d3 > > Please advise. > Thanks, > BR, > Fabrice > On 01/31/2014 06:08 PM, Russell King - ARM Linux wrote: >>> Is it possible to unmask imprecise data aborts earlier in the boot >>> >process (e.g. before PCIe bus enumeration, when drivers are being >>> probed) >>> >? >> How about this patch? >> >> diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c >> index 172ee18ff124..b0ff06f49cd0 100644 >> --- a/arch/arm/kernel/traps.c >> +++ b/arch/arm/kernel/traps.c >> @@ -900,6 +900,15 @@ void __init early_trap_init(void *vectors_base) >> flush_icache_range(vectors, vectors + PAGE_SIZE * 2); >> modify_domain(DOMAIN_USER, DOMAIN_CLIENT); >> + >> + /* Enable imprecise aborts */ >> + asm volatile( >> + "mrs %0, cpsr\n" >> + " bic %0, %0, %1\n" >> + " msr cpsr_c, %0" >> + : "=&r" (i) >> + : "r" (PSR_A_BIT)); >> + >> #else /* ifndef CONFIG_CPU_V7M */ >> /* >> * on V7-M there is no need to copy the vector table to a >> dedicated > diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index dc894ab..e22b109 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -378,6 +378,9 @@ asmlinkage void secondary_start_kernel(void) local_irq_enable(); local_fiq_enable(); + /* Enable imprecise aborts */ + asm volatile("cpsie a"); + /* * OK, it's off to the idle thread for us */ diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 4636d56..a9567bb 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -900,6 +900,10 @@ void __init early_trap_init(void *vectors_base) flush_icache_range(vectors, vectors + PAGE_SIZE * 2); modify_domain(DOMAIN_USER, DOMAIN_CLIENT); + + /* Enable imprecise aborts */ + asm volatile("cpsie a"); + #else /* ifndef CONFIG_CPU_V7M */ /* * on V7-M there is no need to copy the vector table to a dedicated