From patchwork Thu Feb 5 17:16:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsahee Zidenberg X-Patchwork-Id: 5785871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 801A09F336 for ; Thu, 5 Feb 2015 17:18:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E237320270 for ; Thu, 5 Feb 2015 17:18:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09642200DF for ; Thu, 5 Feb 2015 17:18:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YJQ2y-0006KO-8G; Thu, 05 Feb 2015 17:16:56 +0000 Received: from mail-wi0-f180.google.com ([209.85.212.180]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YJQ2T-0005qr-JI for linux-arm-kernel@lists.infradead.org; Thu, 05 Feb 2015 17:16:26 +0000 Received: by mail-wi0-f180.google.com with SMTP id h11so12038640wiw.1 for ; Thu, 05 Feb 2015 09:16:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:user-agent :mime-version:content-type:content-transfer-encoding; bh=9SGusrx2wjixYbRFfZgecasLiQfotr/jadP0yYxdO44=; b=lUhBNY4/L9nlRNKyE6bMEKpqOGYKeMs5VewAM5/iuqVpH/mKNoEROAa3x85LTYuAxQ gkr77kMt89grKx+/A33tNa0J36P7plzPezrNrttLRU+Dx4PIUrWtPMBLYqMVBw/vQsNl LNJc1lKx3j4OH1dYgyIOykHvnkMDLKDXvs87/ubj/At3iGI2MLitW7/OwyZqWlB45KqE MFpg6ko0O7hrp+b9vr9lTH56r6Yoj/tzdrAeAQ/ve8XTNtc5sw77G2VtkGGCMzM2Y+93 Jo28lFs81t9PzUJkTG4OMUskxbyoqE3uRkCZIUh0fQt9Udw5QhB/UTwYkXtlIASwLW65 W+qg== X-Gm-Message-State: ALoCoQlkonHZMkf2z8leBlAgntpRGL7WXLoQW+jfFwjWqDr/dbk8V84CFO9t1dDv72bTeYQfy5UP X-Received: by 10.194.185.15 with SMTP id ey15mr10042027wjc.3.1423156563556; Thu, 05 Feb 2015 09:16:03 -0800 (PST) Received: from localhost ([82.166.183.244]) by mx.google.com with ESMTPSA id x6sm8208734wjf.24.2015.02.05.09.16.02 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 05 Feb 2015 09:16:02 -0800 (PST) Date: Thu, 05 Feb 2015 19:16:00 +0200 From: Tsahee Zidenberg To: arm@kernel.org, linux-arm-kernel@lists.infradead.org, barak@annapurnalabs.com, saeed@annapurnalabs.com Subject: [PATCH v5 4/6] ARM: dts: Alpine platform binding documentation Message-ID: <54d3a550.zTQ3r6+qTRxfdEnC%tsahee@annapurnalabs.com> User-Agent: Heirloom mailx 12.5 6/20/10 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150205_091625_790235_11178840 X-CRM114-Status: GOOD ( 11.49 ) X-Spam-Score: -0.7 (/) Cc: mark.rutland@arm.com, sboyd@codeaurora.org, zeev@annapurnalabs.com, rshitrit@annapurnalabs.com, olof@lixom.net, maxime.coquelin@st.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch introduces documentation for alpine devicetree bindings. Signed-off-by: Barak Wasserstrom Signed-off-by: Tsahee Zidenberg Acked-by: Arnd Bergmann --- .../devicetree/bindings/arm/al,alpine.txt | 88 ++++++++++++++++++++++ .../bindings/arm/cpu-enable-method/al,alpine-smp | 52 +++++++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + 3 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/al,alpine.txt create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp diff --git a/Documentation/devicetree/bindings/arm/al,alpine.txt b/Documentation/devicetree/bindings/arm/al,alpine.txt new file mode 100644 index 0000000..3dbd9bd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/al,alpine.txt @@ -0,0 +1,88 @@ +Annapurna Labs Alpine Platform Device Tree Bindings +--------------------------------------------------------------- + +Boards in the Alpine family shall have the following properties: + +* Required root node properties: +compatible: must contain "al,alpine" + +* Example: + +/ { + model = "Annapurna Labs Alpine Dev Board"; + compatible = "al,alpine"; + + ... +} + +* CPU node: + +The Alpine platform includes cortex-a15 cores. +enable-method: must be "al,alpine-smp" to allow smp [1] + +Example: + +cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "al,alpine-smp"; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; +}; + + +* Alpine CPU resume registers + +The CPU resume register are used to define required resume address after +reset. + +Properties: +- compatible : Should contain "al,alpine-cpu-resume". +- reg : Offset and length of the register set for the device + +Example: + +cpu_resume { + compatible = "al,alpine-cpu-resume"; + reg = <0xfbff5ed0 0x30>; +}; + +* Alpine System-Fabric Service Registers + +The System-Fabric Service Registers allow various operation on CPU and +system fabric, like powering CPUs off. + +Properties: +- compatible : Should contain "al,alpine-sysfabric-service" and "syscon". +- reg : Offset and length of the register set for the device + +Example: + +nb_service { + compatible = "al,alpine-sysfabric-service", "syscon"; + reg = <0xfb070000 0x10000>; +}; + +[1] arm/cpu-enable-method/al,alpine-smp diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp new file mode 100644 index 0000000..c2e0cc5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp @@ -0,0 +1,52 @@ +======================================================== +Secondary CPU enable-method "al,alpine-smp" binding +======================================================== + +This document describes the "al,alpine-smp" method for +enabling secondary CPUs. To apply to all CPUs, a single +"al,alpine-smp" enable method should be defined in the +"cpus" node. + +Enable method name: "al,alpine-smp" +Compatible machines: "al,alpine" +Compatible CPUs: "arm,cortex-a15" +Related properties: (none) + +Note: +This enable method requires valid nodes compatible with +"al,alpine-cpu-resume" and "al,alpine-nb-service"[1]. + +Example: + +cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "al,alpine-smp"; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; +}; + +-- +[1] arm/al,alpine.txt diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index e02e14d..248532f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -10,6 +10,7 @@ adapteva Adapteva, Inc. adi Analog Devices, Inc. aeroflexgaisler Aeroflex Gaisler AB ak Asahi Kasei Corp. +al Annapurna Labs allwinner Allwinner Technology Co., Ltd. alphascale AlphaScale Integrated Circuits Systems, Inc. altr Altera Corp.