From patchwork Wed Mar 18 11:58:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 6038431 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 94DB99F444 for ; Wed, 18 Mar 2015 12:02:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B4726204D5 for ; Wed, 18 Mar 2015 12:02:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C691C20465 for ; Wed, 18 Mar 2015 12:02:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YYCdG-0001mK-Gk; Wed, 18 Mar 2015 11:59:30 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YYCdB-0001i1-Sm for linux-arm-kernel@lists.infradead.org; Wed, 18 Mar 2015 11:59:26 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t2IBx1Dx005571; Wed, 18 Mar 2015 06:59:01 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t2IBx0PN024629; Wed, 18 Mar 2015 06:59:00 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Wed, 18 Mar 2015 06:59:00 -0500 Received: from [172.24.190.171] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t2IBwvlA018428; Wed, 18 Mar 2015 06:58:58 -0500 Message-ID: <55096881.9040506@ti.com> Date: Wed, 18 Mar 2015 17:28:57 +0530 From: Sekhar Nori User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Peter Ujfalusi , Subject: Re: [RESEND 6/7] ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x References: <1426147591-31764-1-git-send-email-peter.ujfalusi@ti.com> <1426147591-31764-7-git-send-email-peter.ujfalusi@ti.com> In-Reply-To: <1426147591-31764-7-git-send-email-peter.ujfalusi@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150318_045926_099977_965CBDBE X-CRM114-Status: GOOD ( 11.93 ) X-Spam-Score: -5.0 (-----) Cc: arm@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thursday 12 March 2015 01:36 PM, Peter Ujfalusi wrote: > McASP1 TX interrupt is 30, not 32 on DM646x DMSoC > > Signed-off-by: Peter Ujfalusi Okay, sparse spotted an error uncovered by this patch. I think it will be good to fix that as well here. Updated patch attached. Thanks, Sekhar ---8<--- From: Peter Ujfalusi Date: Thu, 12 Mar 2015 10:06:30 +0200 Subject: [PATCH] ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x McASP1 TX interrupt is 30, not 32 on DM646x DMSoC. While at it remove the bogus AEMIF interrupt entry from dm646x_default_priorities[]. AEMIF interrupt on DM6467 is 60 not 30 and the entry for the correct interrupt number is already present in the same table. Signed-off-by: Peter Ujfalusi [nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]] Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/dm646x.c | 1 - arch/arm/mach-davinci/include/mach/irqs.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index d2a2619aee81..58769eddd3c3 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { [IRQ_DM646X_EMACMISCINT] = 7, [IRQ_DM646X_MCASP0TXINT] = 7, [IRQ_DM646X_MCASP0RXINT] = 7, - [IRQ_AEMIFINT] = 7, [IRQ_DM646X_RESERVED_3] = 7, [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ [IRQ_TINT0_TINT34] = 7, /* clocksource */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 354af71798dc..edb2ca62321a 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -129,8 +129,8 @@ #define IRQ_DM646X_EMACMISCINT 27 #define IRQ_DM646X_MCASP0TXINT 28 #define IRQ_DM646X_MCASP0RXINT 29 +#define IRQ_DM646X_MCASP1TXINT 30 #define IRQ_DM646X_RESERVED_3 31 -#define IRQ_DM646X_MCASP1TXINT 32 #define IRQ_DM646X_VLQINT 38 #define IRQ_DM646X_UARTINT2 42 #define IRQ_DM646X_SPINT0 43