From patchwork Tue Jul 14 11:59:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 6786761 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CDFE79F2F0 for ; Tue, 14 Jul 2015 12:02:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EB3CC206CD for ; Tue, 14 Jul 2015 12:02:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18142206BA for ; Tue, 14 Jul 2015 12:02:11 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEyrz-0005pZ-J3; Tue, 14 Jul 2015 11:59:31 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZEyrx-0005oD-IU for linux-arm-kernel@lists.infradead.org; Tue, 14 Jul 2015 11:59:29 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 14 Jul 2015 04:59:40 -0700 Received: from HQMAIL105.nvidia.com ([172.20.187.12]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 14 Jul 2015 04:59:08 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 14 Jul 2015 04:59:08 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 14 Jul 2015 11:59:07 +0000 Received: from [10.21.132.102] (10.21.132.102) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 14 Jul 2015 11:59:02 +0000 Message-ID: <55A4F985.7010503@nvidia.com> Date: Tue, 14 Jul 2015 12:59:01 +0100 From: Jon Hunter User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Peter De Schrijver Subject: Re: [PATCH V3 06/19] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 References: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> <1436791197-32358-7-git-send-email-jonathanh@nvidia.com> <20150713134151.GQ6287@tbergstrom-lnx.Nvidia.com> <55A3C50E.7060706@nvidia.com> In-Reply-To: <55A3C50E.7060706@nvidia.com> X-Originating-IP: [10.21.132.102] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150714_045929_627758_0E3C1036 X-CRM114-Status: GOOD ( 18.25 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Courbot , Ulf Hansson , Prashant Gaikwad , =?windows-1252?Q?Terje_Bergstr?= =?windows-1252?Q?=F6m?= , Vince Hsu , Stephen Warren , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Kevin Hilman , "Rafael J. Wysocki" , Hans de Goede , devicetree@vger.kernel.org, Thierry Reding , Philipp Zabel , Tejun Heo , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 13/07/15 15:02, Jon Hunter wrote: > > > On 13/07/15 14:41, Peter De Schrijver wrote: >> On Mon, Jul 13, 2015 at 01:39:44PM +0100, Jon Hunter wrote: >>> From: Vince Hsu >>> >>> Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when >>> the DIS power domain is during up-powergating process but the clamp to this >> >> I think there is missing 'off' in this sentence? >> >> ie. ... 'the DIS power domain is off during up-powergating process' >> >> Also 'un-powergating sequence' would be nicer. > > Yes agree. I will re-word that. Updated version ... From d5cbecd4e97332cd8373b9c4893731eb8e063660 Mon Sep 17 00:00:00 2001 From: Vince Hsu Date: Wed, 11 Mar 2015 16:46:04 +0800 Subject: [PATCH 06/19] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 Tegra114 has a HW bug where the PLLD/PLLD2 lock bit cannot be asserted while turning on the Display power domain and before the clamp to this domain has been removed. This issue causes a timeout and aborts the power up sequence, even though the PLLD/PLLD2 has already locked. To avoid this, don't use the lock for PLLD/PLLD2, just wait 1ms and treat the clocks as locked. Signed-off-by: Vince Hsu [jonathanh@nvidia.com: Updated the changelog description] Signed-off-by: Jon Hunter Acked-By: Peter De Schrijver --- drivers/clk/tegra/clk-tegra114.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 8237d16b4075..2e5c20c7c088 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -456,8 +456,7 @@ static struct tegra_clk_pll_params pll_d_params = { .lock_delay = 1000, .div_nmp = &pllp_nmp, .freq_table = pll_d_freq_table, - .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | - TEGRA_PLL_USE_LOCK, + .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON, }; static struct tegra_clk_pll_params pll_d2_params = { @@ -474,8 +473,7 @@ static struct tegra_clk_pll_params pll_d2_params = { .lock_delay = 1000, .div_nmp = &pllp_nmp, .freq_table = pll_d_freq_table, - .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | - TEGRA_PLL_USE_LOCK, + .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON, }; static struct pdiv_map pllu_p[] = {