From patchwork Tue Jul 28 15:30:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 6887471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 05493C05AC for ; Tue, 28 Jul 2015 15:33:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8243F20600 for ; Tue, 28 Jul 2015 15:33:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8D701205FF for ; Tue, 28 Jul 2015 15:33:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZK6ql-0002TT-4f; Tue, 28 Jul 2015 15:31:27 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZK6qh-0002GG-68 for linux-arm-kernel@lists.infradead.org; Tue, 28 Jul 2015 15:31:23 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 28 Jul 2015 08:31:42 -0700 Received: from HQMAIL103.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 28 Jul 2015 08:29:04 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 28 Jul 2015 08:29:04 -0700 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 28 Jul 2015 15:31:00 +0000 Received: from [10.21.132.159] (10.21.132.159) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 28 Jul 2015 15:30:56 +0000 Message-ID: <55B7A02E.40506@nvidia.com> Date: Tue, 28 Jul 2015 16:30:54 +0100 From: Jon Hunter User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Thierry Reding Subject: Re: [PATCH V3 10/19] drm/tegra: dc: Prepare for generic PM domains References: <1436791197-32358-1-git-send-email-jonathanh@nvidia.com> <1436791197-32358-11-git-send-email-jonathanh@nvidia.com> <20150717104154.GM3057@ulmo> <55B73D8C.103@nvidia.com> <20150728112030.GA10949@ulmo.nvidia.com> In-Reply-To: <20150728112030.GA10949@ulmo.nvidia.com> X-Originating-IP: [10.21.132.159] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150728_083123_274902_43B3C01C X-CRM114-Status: GOOD ( 20.54 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Courbot , Ulf Hansson , Prashant Gaikwad , =?windows-1252?Q?Terje_Bergstr?= =?windows-1252?Q?=F6m?= , Vince Hsu , Stephen Warren , linux-tegra@vger.kernel.org, Peter De Schrijver , Kevin Hilman , "Rafael J. Wysocki" , Hans de Goede , devicetree@vger.kernel.org, Philipp Zabel , linux-pm@vger.kernel.org, Tejun Heo , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 28/07/15 12:20, Thierry Reding wrote: > On Tue, Jul 28, 2015 at 09:30:04AM +0100, Jon Hunter wrote: >> May be that would be a cleaner transition than trying to do it all in >> one go. > > I have a couple of patches in my tree to do this for DRM as part of an > effort to restore DPMS. It's fairly tricky to get right in DRM and > requires all sorts of changes to the driver. Hmmm ... I was just thinking about moving what is currently there in the pm-runtime helpers ... diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index a287e4fec865..0f1dc01215b1 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -1922,29 +1923,12 @@ static int tegra_dc_probe(struct platform_device *pdev) dc->powergate = TEGRA_POWERGATE_DIS; else dc->powergate = TEGRA_POWERGATE_DISB; + } - err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, - dc->rst); - if (err < 0) { - dev_err(&pdev->dev, "failed to power partition: %d\n", - err); - return err; - } - } else { - err = clk_prepare_enable(dc->clk); - if (err < 0) { - dev_err(&pdev->dev, "failed to enable clock: %d\n", - err); - return err; - } + platform_set_drvdata(pdev, dc); - err = reset_control_deassert(dc->rst); - if (err < 0) { - dev_err(&pdev->dev, "failed to deassert reset: %d\n", - err); - return err; - } - } + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); dc->regs = devm_ioremap_resource(&pdev->dev, regs); @@ -1978,8 +1962,6 @@ static int tegra_dc_probe(struct platform_device *pdev) if (!dc->syncpt) dev_warn(&pdev->dev, "failed to allocate syncpoint\n"); - platform_set_drvdata(pdev, dc); - return 0; } @@ -2003,6 +1985,17 @@ static int tegra_dc_remove(struct platform_device *pdev) return err; } + pm_runtime_put(&pdev->dev); + + return 0; +} + +#ifdef CONFIG_PM +static int tegra_dc_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct tegra_dc *dc = platform_get_drvdata(pdev); + reset_control_assert(dc->rst); if (dc->soc->has_powergate) @@ -2013,11 +2006,54 @@ static int tegra_dc_remove(struct platform_device *pdev) return 0; } +static int tegra_dc_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct tegra_dc *dc = platform_get_drvdata(pdev); + int err; + + if (dc->soc->has_powergate) { + err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, + dc->rst); + if (err < 0) { + dev_err(&pdev->dev, "failed to power partition: %d\n", + err); + return err; + } + } else { + err = clk_prepare_enable(dc->clk); + if (err < 0) { + dev_err(&pdev->dev, "failed to enable clock: %d\n", + err); + return err; + } + + err = reset_control_deassert(dc->rst); + if (err < 0) { + dev_err(&pdev->dev, "failed to deassert reset: %d\n", + err); + return err; + } + } + + return 0; +} + +static struct dev_pm_ops tegra_dc_pm_ops = { + SET_RUNTIME_PM_OPS(tegra_dc_runtime_suspend, + tegra_dc_runtime_resume, NULL) +}; +#define TEGRA_DC_PM_OPS (&tegra_dc_pm_ops) +#else +#define TEGRA_DC_PM_OPS NULL +#endif /* CONFIG_PM */ + struct platform_driver tegra_dc_driver = { .driver = { .name = "tegra-dc", .owner = THIS_MODULE, .of_match_table = tegra_dc_of_match, + .pm = TEGRA_DC_PM_OPS, }, .probe = tegra_dc_probe, .remove = tegra_dc_remove,