From patchwork Mon Dec 7 13:09:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 7783711 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2B3319F39B for ; Mon, 7 Dec 2015 13:12:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5C6BB203DC for ; Mon, 7 Dec 2015 13:12:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3CB6C203DB for ; Mon, 7 Dec 2015 13:12:08 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a5vYO-0004bW-6n; Mon, 07 Dec 2015 13:10:08 +0000 Received: from eu-smtp-delivery-143.mimecast.com ([207.82.80.143]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a5vYK-0003pk-Hb for linux-arm-kernel@lists.infradead.org; Mon, 07 Dec 2015 13:10:05 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-8-x5ljd0jfQ9m4Yf1-AN0hUA-1; Mon, 07 Dec 2015 13:09:36 +0000 Received: from [10.1.205.33] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 7 Dec 2015 13:09:36 +0000 Subject: Re: [PATCH 3/5] iommu/arm-smmu: Invalidate TLBs properly To: Will Deacon References: <2acaea8656f14a4421d7d466dd242fe5a3d0f6f6.1449246988.git.robin.murphy@arm.com> <20151207110939.GB23430@arm.com> From: Robin Murphy Message-ID: <5665850F.1060406@arm.com> Date: Mon, 7 Dec 2015 13:09:35 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20151207110939.GB23430@arm.com> X-OriginalArrivalTime: 07 Dec 2015 13:09:36.0057 (UTC) FILETIME=[85811A90:01D130F0] X-MC-Unique: x5ljd0jfQ9m4Yf1-AN0hUA-1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151207_051004_898292_9B84DACF X-CRM114-Status: GOOD ( 13.00 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.pinchart+renesas@ideasonboard.com, joro@8bytes.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, mitchelh@codeaurora.org, brian.starkey@arm.com, yong.wu@mediatek.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 07/12/15 11:09, Will Deacon wrote: > On Fri, Dec 04, 2015 at 05:53:00PM +0000, Robin Murphy wrote: >> When invalidating an IOVA range potentially spanning multiple pages, >> such as when removing an entire intermediate-level table, we currently >> only issue an invalidation for the first IOVA of that range. Since the >> architecture specifies that address-based TLB maintenance operations >> target a single entry, an SMMU could feasibly retain live entries for >> subsequent pages within that unmapped range, which is not good. >> >> Make sure we hit every possible entry by iterating over the whole range >> at the granularity provided by the pagetable implementation. >> >> Signed-off-by: Robin Murphy >> --- >> drivers/iommu/arm-smmu.c | 19 ++++++++++++++++--- >> 1 file changed, 16 insertions(+), 3 deletions(-) > > Can you do something similar for arm-smmu-v3.c as well, please? Something like this? (untested as I don't have a v3 model set up): ------>8------ From: Robin Murphy Date: Mon, 7 Dec 2015 12:52:56 +0000 Subject: [PATCH] iommu/arm-smmu: Fix TLB invalidation SMMUv3 operates under the same rules as SMMUv2 and the CPU architectures, so when invalidating an IOVA range we have to hit every address for which a TLB entry might exist. To fix this, issue commands for the whole range rather than just the initial address; as a minor optimisation, try to avoid flooding the queue by falling back to 'invalidate all' if the range is large. Signed-off-by: Robin Murphy --- drivers/iommu/arm-smmu-v3.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; @@ -1354,7 +1358,10 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; } - arm_smmu_cmdq_issue_cmd(smmu, &cmd); + do { + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + cmd.tlbi.addr += granule; + } while (size -= granule); } static struct iommu_gather_ops arm_smmu_gather_ops = { diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index c302b65..afa0b41 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -1346,6 +1346,10 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, }, }; + /* If we'd fill the whole queue or more, don't even bother... */ + if (granule << smmu->cmdq.q.max_n_shift >= size / (CMDQ_ENT_DWORDS << 3)) + return arm_smmu_tlb_inv_context(cookie); + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { cmd.opcode = CMDQ_OP_TLBI_NH_VA;