From patchwork Tue Dec 8 18:50:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Behme X-Patchwork-Id: 7801421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 038B79F1C2 for ; Tue, 8 Dec 2015 18:53:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2EEF62040F for ; Tue, 8 Dec 2015 18:52:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D436203B0 for ; Tue, 8 Dec 2015 18:52:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6NM0-0005Ag-0b; Tue, 08 Dec 2015 18:51:12 +0000 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6NLw-0004yk-Ll for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2015 18:51:09 +0000 Received: by wmww144 with SMTP id w144so7303839wmw.1 for ; Tue, 08 Dec 2015 10:50:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=subject:to:references:cc:from:message-id:date:user-agent :mime-version:in-reply-to:content-type:content-transfer-encoding; bh=gzXW1w+5DVYD8NFEhlCkFctg8Wdt1IhgGjDX/S3mZmk=; b=Y2L9a6rZOHCBU7Hef+dbXpZwOr8MaOKSLwCSyvH/qyWQ/Fb2ybU5V/oyo/M3NrDjh8 286csvbGhkKvoul1xjtmls7bqIGcEpOIoETV3zmItuo7tmQEUGoMXuN30fMU7+OQ58Vs 6AKDsDWB5+VfQ2Xc20oS5WMVcUyOA/xJK3K/zah5Q+p+kQYO/aW/BqYdBGDdPGHFTcVh OekI/lov8DnkmpToOZgdn6GLstRAY1hwfJ/kslkYTYsWslgZt4gB7buIiNM9P+0vc8rB VIprUOOzSuEV4oFvCbi4X0b6pT0/gXPJTYuzfhgdN96QCGzl9ASAlYy22Q8JEG84xt5x xegA== X-Received: by 10.28.97.10 with SMTP id v10mr30709973wmb.66.1449600646527; Tue, 08 Dec 2015 10:50:46 -0800 (PST) Received: from [192.168.178.36] (p4FEE0C93.dip0.t-ipconnect.de. [79.238.12.147]) by smtp.gmail.com with ESMTPSA id u17sm4658454wmd.8.2015.12.08.10.50.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Dec 2015 10:50:45 -0800 (PST) Subject: Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes To: Mark Rutland , Sudeep Holla References: <1449512659-16688-1-git-send-email-geert+renesas@glider.be> <1449512659-16688-7-git-send-email-geert+renesas@glider.be> <5665D4C7.1050705@arm.com> <20151207190355.GE28024@leverpostej> From: Dirk Behme Message-ID: <5667267E.2080601@gmail.com> Date: Tue, 8 Dec 2015 19:50:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20151207190355.GE28024@leverpostej> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151208_105109_057254_E8DF07F5 X-CRM114-Status: GOOD ( 17.11 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Pawel Moll , Simon Horman , Ian Campbell , Catalin Marinas , linux-pm@vger.kernel.org, linux-sh@vger.kernel.org, Magnus Damm , Will Deacon , Rob Herring , linux-arm-kernel@lists.infradead.org, Kumar Gala , Geert Uytterhoeven , Lina Iyer Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 07.12.2015 20:03, Mark Rutland wrote: > On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote: >> >> On 07/12/15 18:24, Geert Uytterhoeven wrote: >>> + L2_CA57: cache-controller@0 { >>> + compatible = "cache"; >>> + arm,data-latency = <4 4 1>; >>> + arm,tag-latency = <3 3 3>; >> >> Interesting, only PL2xx/3xx cache controller driver reads this from the >> DT and configures the controller. The integrated L2 found in >> A15/A7/A57/A53 needs doesn't make use of these values from the DT. > > These properties seem to be from l2cc.txt, which really only corresponds > to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds. > > I don't see that these are necessary at all. What's about a documentation patch like [1], then? For what is the arm64 dts entry cpu@0 { ... next-level-cache = <&L2_0>; }; L2_0: l2-cache0 { compatible = "cache"; }; good for at all, then? Best regards Dirk [1] +preconfigured by early secure boot code. + +The ARM L2 cache representation for 32-bit cores in the device tree should be done +as follows: Required properties: diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index 06c88a4..f687aed 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -1,12 +1,18 @@ * ARM L2 Cache Controller -ARM cores often have a separate level 2 cache controller. There are various +ARM 32-bit cores often have a separate level 2 cache controller. There are various implementations of the L2 cache controller with compatible programming models. Some of the properties that are just prefixed "cache-*" are taken from section 3.7.3 of the ePAPR v1.1 specification which can be found at: https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf -The ARM L2 cache representation in the device tree should be done as follows: +ARM 64-bit cores (e.g. A15/A7/A57/A53) have an integrated level 2 cache which +doesn't make use of any values from the kernel device tree. There is no +L2 cache configuration done in the kernel. The L2 cache is assumed to be