From patchwork Thu Jan 7 13:19:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 7977401 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 21294BEEE5 for ; Thu, 7 Jan 2016 13:22:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 32A7C201BB for ; Thu, 7 Jan 2016 13:22:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 490E720172 for ; Thu, 7 Jan 2016 13:22:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aHAUC-0003mU-MA; Thu, 07 Jan 2016 13:20:16 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aHAU9-0002aO-7O for linux-arm-kernel@lists.infradead.org; Thu, 07 Jan 2016 13:20:14 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 07 Jan 2016 05:20:16 -0800 Received: from HQMAIL104.nvidia.com ([172.18.146.11]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 07 Jan 2016 05:15:34 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 07 Jan 2016 05:15:34 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1104.5; Thu, 7 Jan 2016 13:19:50 +0000 Received: from [10.21.132.159] (10.21.132.159) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1104.5; Thu, 7 Jan 2016 13:19:46 +0000 Subject: Re: [PATCH] ARM64: tegra: Add support for Google Pixel C To: Mark Rutland , Arnd Bergmann References: <1452073222-2956-1-git-send-email-jonathanh@nvidia.com> <20160106094616.GA563@leverpostej> <568D0D70.4020309@nvidia.com> From: Jon Hunter Message-ID: <568E65F0.2070201@nvidia.com> Date: Thu, 7 Jan 2016 13:19:44 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <568D0D70.4020309@nvidia.com> X-Originating-IP: [10.21.132.159] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160107_052013_414709_140669D7 X-CRM114-Status: GOOD ( 16.98 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Courbot , Pawel Moll , Stephen Warren , Ian Campbell , devicetree@vger.kernel.org, Rob Herring , Thierry Reding , Kumar Gala , linux-tegra@vger.kernel.org, Olof Johansson , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 06/01/16 12:49, Jon Hunter wrote: > On 06/01/16 09:46, Mark Rutland wrote: >> Hi, >> >> On Wed, Jan 06, 2016 at 09:40:22AM +0000, Jon Hunter wrote: >>> Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based >>> upon Tegra210 SoC with 3 GiB of LPDDR4 RAM. >>> >>> Signed-off-by: Jon Hunter >>> --- >>> arch/arm64/boot/dts/nvidia/Makefile | 1 + >>> arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 42 +++++++++++++++++++++++++++ >>> 2 files changed, 43 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts [snip] >>> + >>> + chosen { >>> + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x70006000"; >>> + }; >> >> Use stdout-path. > > Ok. Adding Arnd. Hmmm ... well apparently stdout-path does not work for tegra and in order to make this work I had to do the following ... [PATCH] serial: 8250: of: Add earlycon support for Tegra Currently, early console support only works for Tegra when the serial port information is passed via the earlycon boot parameter. If the serial port information is specified via device-tree using the "stdout-path" then the early console does not work because: 1. The tegra serial ports compatibility parameter does not match any of the supported serial drivers for early console. 2. The of_setup_earlycon() function assumes that serial port registers are byte aligned and for tegra they are 32-bit aligned. Add an early console setup function for tegra so that the early console can be specified via the device-tree "stdout-path" variable. Signed-off-by: Jon Hunter --- drivers/tty/serial/8250/8250_of.c | 10 ++++++++++ 1 file changed, 10 insertions(+) Arnd, does the above look ok, or should there be a generic early_serial8250x32_setup() somewhere? Cheers Jon diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c index 33021c1f7d55..98adf83e83c2 100644 --- a/drivers/tty/serial/8250/8250_of.c +++ b/drivers/tty/serial/8250/8250_of.c @@ -44,6 +44,16 @@ void tegra_serial_handle_break(struct uart_port *p) udelay(1); } while (1); } + +int __init tegra_earlycon_setup(struct earlycon_device *device, + const char *options) +{ + device->port.iotype = UPIO_MEM32; + device->port.regshift = 2; + + return early_serial8250_setup(device, options); +} +OF_EARLYCON_DECLARE(tegra20_uart, "nvidia,tegra20-uart", tegra_earlycon_setup); #else static inline void tegra_serial_handle_break(struct uart_port *port) {