From patchwork Sun Jun 19 04:15:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: khiemnguyen X-Patchwork-Id: 9186059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 44699601C0 for ; Sun, 19 Jun 2016 04:17:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D3092774A for ; Sun, 19 Jun 2016 04:17:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1F8F027C2C; Sun, 19 Jun 2016 04:17:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9C4DF2774A for ; Sun, 19 Jun 2016 04:17:43 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bEU9V-0004VD-RP; Sun, 19 Jun 2016 04:16:05 +0000 Received: from relmlor2.renesas.com ([210.160.252.172] helo=relmlie1.idc.renesas.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bEU9S-0004Lu-5w for linux-arm-kernel@lists.infradead.org; Sun, 19 Jun 2016 04:16:03 +0000 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie1.idc.renesas.com with ESMTP; 19 Jun 2016 13:15:40 +0900 Received: from relmlac1.idc.renesas.com (relmlac1.idc.renesas.com [10.200.69.21]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 781BE3D346 for ; Sun, 19 Jun 2016 13:15:40 +0900 (JST) Received: by relmlac1.idc.renesas.com (Postfix, from userid 0) id 6D8548002F; Sun, 19 Jun 2016 13:15:40 +0900 (JST) Received: from relmlac1.idc.renesas.com (localhost [127.0.0.1]) by relmlac1.idc.renesas.com (Postfix) with ESMTP id 6D3368002E for ; Sun, 19 Jun 2016 13:15:40 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac1.idc.renesas.com with ESMTP id PAD04447; Sun, 19 Jun 2016 13:15:40 +0900 X-IronPort-AV: E=Sophos;i="5.22,559,1449500400"; d="scan'208";a="213273534" Received: from unknown (HELO outside-ironport.rvc.renesas.com) ([172.29.139.110]) by relmlii1.idc.renesas.com with ESMTP; 19 Jun 2016 13:15:39 +0900 Received: from rvc-hts-01.rvc.renesas.com ([172.29.139.122]) by inside-ironport.rvc.renesas.com with ESMTP; 19 Jun 2016 11:15:39 +0700 Received: from [172.29.157.15] (172.29.157.15) by rvc-hts-01.rvc.renesas.com (172.29.139.120) with Microsoft SMTP Server id 8.3.83.0; Sun, 19 Jun 2016 11:15:39 +0700 Subject: [PATCH/RFC 2/3] thermal: rcar_gen3_thermal: Modify the way to detect the interrupts To: Kuninori Morimoto References: <57661211.7010900@rvc.renesas.com> <57661BB1.3060401@rvc.renesas.com> From: Khiem Nguyen Message-ID: <57661C6A.5050300@rvc.renesas.com> Date: Sun, 19 Jun 2016 11:15:38 +0700 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <57661BB1.3060401@rvc.renesas.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160618_211602_575988_78A90F86 X-CRM114-Status: GOOD ( 14.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Simon Horman , "devicetree@vger.kernel.org" , "Hien Duy. Dang" , Geert Uytterhoeven , Wolfram Sang , Catalin Marinas , "linux-pm@vger.kernel.org" , Magnus Damm , "linux-kernel@vger.kernel.org" , Eduardo Valentin , Rob Herring , Toru Oishi , "Khiem Trong. Nguyen" , "linux-renesas-soc@vger.kernel.org" , Gaku Inami , Zhang Rui , "Thao Phuong Le. Nguyen" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The current implementation is that the interrupt I/F and thermal sensor are assigned with one-to-one. So it can't be set the more interrupt trigger to one thermal sensor. Also, the interrupt is detected by a little bit change in temperature. In order to solve the above problems, the interrupt of thermal sensor is changed as below. - Change the shared interrupt in each thermal sensors. - Detect the interrupt when the temperature is changed one degree up and down. Signed-off-by: Gaku Inami Signed-off-by: Khiem Nguyen --- drivers/thermal/rcar_gen3_thermal.c | 69 +++++++++++++++++++++++-------------- 1 file changed, 44 insertions(+), 25 deletions(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index e640a14..dc5f231 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -63,6 +63,11 @@ #define CTEMP_MASK 0xFFF +#define IRQ_TEMP1_BIT (0x1 << 0) +#define IRQ_TEMP2_BIT (0x1 << 1) +#define IRQ_TEMPD1_BIT (0x1 << 3) +#define IRQ_TEMPD2_BIT (0x1 << 4) + #define MCELSIUS(temp) ((temp) * 1000) #define TEMP_IRQ_SHIFT(tsc_id) (0x1 << tsc_id) #define TEMPD_IRQ_SHIFT(tsc_id) (0x1 << (tsc_id + 3)) @@ -216,28 +221,42 @@ int _linear_temp_converter(struct equation_coefs coef, return _round_temp(temp); } +int _linear_celsius_to_temp(struct equation_coefs coef, + int ctemp) +{ + int temp_code, temp1, temp2; + + temp1 = (ctemp * coef.a1 / 1000 + coef.b1) / 1000; + temp2 = (ctemp * coef.a2 / 1000 + coef.b2) / 1000; + temp_code = (temp1 + temp2) / 2; + + return temp_code; +} + /* * Zone device functions */ static int rcar_gen3_thermal_update_temp(struct rcar_gen3_thermal_priv *priv) { u32 ctemp; - int i; unsigned long flags; - u32 reg = REG_GEN3_IRQTEMP1 + (priv->id * 4); + int temp_cel, temp_code; spin_lock_irqsave(&priv->lock, flags); - for (i = 0; i < 256; i++) { - ctemp = thermal_reg_read(priv, REG_GEN3_TEMP) & CTEMP_MASK; - if (rcar_has_irq_support(priv)) { - thermal_reg_write(priv, reg, ctemp); - if (thermal_reg_read(priv, REG_GEN3_IRQSTR) != 0) - break; - } else - break; + ctemp = thermal_reg_read(priv, REG_GEN3_TEMP) & CTEMP_MASK; + if (rcar_has_irq_support(priv)) { + temp_cel = _linear_temp_converter(priv->coef, ctemp); + + /* set the interrupts to exceed the temperature */ + temp_code = _linear_celsius_to_temp(priv->coef, + temp_cel + MCELSIUS(1)); + thermal_reg_write(priv, REG_GEN3_IRQTEMP1, temp_code); - udelay(150); + /* set the interrupts to fall below the temperature */ + temp_code = _linear_celsius_to_temp(priv->coef, + temp_cel - MCELSIUS(1)); + thermal_reg_write(priv, REG_GEN3_IRQTEMP2, temp_code); } priv->ctemp = ctemp; @@ -283,14 +302,14 @@ static int r8a7795_thermal_init(struct rcar_gen3_thermal_priv *priv) thermal_reg_write(priv, REG_GEN3_CTSR, PONM); thermal_reg_write(priv, REG_GEN3_IRQCTL, 0x3F); - thermal_reg_write(priv, REG_GEN3_IRQEN, TEMP_IRQ_SHIFT(priv->id) | - TEMPD_IRQ_SHIFT(priv->id)); + thermal_reg_write(priv, REG_GEN3_IRQEN, + IRQ_TEMP1_BIT | IRQ_TEMPD2_BIT); thermal_reg_write(priv, REG_GEN3_CTSR, - PONM | AOUT | THBGR | VMEN); + PONM | AOUT | THBGR | VMEN); udelay(100); thermal_reg_write(priv, REG_GEN3_CTSR, - PONM | AOUT | THBGR | VMEN | VMST | THSST); + PONM | AOUT | THBGR | VMEN | VMST | THSST); spin_unlock_irqrestore(&priv->lock, flags); @@ -305,11 +324,11 @@ static int r8a7796_thermal_init(struct rcar_gen3_thermal_priv *priv) spin_lock_irqsave(&priv->lock, flags); thermal_reg_write(priv, REG_GEN3_THCTR, 0x0); udelay(1000); + thermal_reg_write(priv, REG_GEN3_IRQCTL, 0x3F); - thermal_reg_write(priv, REG_GEN3_IRQEN, TEMP_IRQ_SHIFT(priv->id) | - TEMPD_IRQ_SHIFT(priv->id)); - thermal_reg_write(priv, REG_GEN3_THCTR, - CTCTL | THCNTSEN(BIT_LEN_12)); + thermal_reg_write(priv, REG_GEN3_IRQEN, + IRQ_TEMP1_BIT | IRQ_TEMPD2_BIT); + thermal_reg_write(priv, REG_GEN3_THCTR, CTCTL | THCNTSEN(BIT_LEN_12)); reg_val = thermal_reg_read(priv, REG_GEN3_THCTR); reg_val &= ~CTCTL; reg_val |= THSST; @@ -334,8 +353,7 @@ static void _thermal_irq_ctrl(struct rcar_gen3_thermal_priv *priv, int enable) spin_lock_irqsave(&priv->lock, flags); thermal_reg_write(priv, REG_GEN3_IRQMSK, - enable ? (TEMP_IRQ_SHIFT(priv->id) | - TEMPD_IRQ_SHIFT(priv->id)) : 0); + enable ? (IRQ_TEMP1_BIT | IRQ_TEMPD2_BIT) : 0); spin_unlock_irqrestore(&priv->lock, flags); } @@ -361,11 +379,12 @@ static irqreturn_t rcar_gen3_thermal_irq(int irq, void *data) thermal_reg_write(priv, REG_GEN3_IRQSTR, 0); spin_unlock_irqrestore(&priv->lock, flags); - if ((status & TEMP_IRQ_SHIFT(priv->id)) || - (status & TEMPD_IRQ_SHIFT(priv->id))) { + if (status == 0) + return IRQ_NONE; + + if (status & (IRQ_TEMP1_BIT | IRQ_TEMPD2_BIT)) { rcar_gen3_thermal_irq_disable(priv); - schedule_delayed_work(&priv->work, - msecs_to_jiffies(300)); + schedule_delayed_work(&priv->work, 0); } return IRQ_HANDLED;