Message ID | 577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2] clk: meson: g12a: mark fclk_div2 as critical | expand |
On Fri 28 Aug 2020 at 17:52, Stefan Agner <stefan@agner.ch> wrote: > On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2 > seems to be necessary for the system to operate correctly as well. > > Typically, the clock also gets chosen by the eMMC peripheral. This > probably masked the problem so far. However, when booting from a SD > card the clock seems to get disabled which leads to a system freeze. > > Let's mark this clock as critical, fixing boot from SD card on G12b > platforms. > > Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") > Cc: Marek Szyprowski <m.szyprowski@samsung.com> > Signed-off-by: Stefan Agner <stefan@agner.ch> > Tested-by: Anand Moon <linux.amoon@gmail.com> Applied Thx. > --- > drivers/clk/meson/g12a.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c > index fad616cac01e..6d44cadc06af 100644 > --- a/drivers/clk/meson/g12a.c > +++ b/drivers/clk/meson/g12a.c > @@ -298,6 +298,17 @@ static struct clk_regmap g12a_fclk_div2 = { > &g12a_fclk_div2_div.hw > }, > .num_parents = 1, > + /* > + * Similar to fclk_div3, it seems that this clock is used by > + * the resident firmware and is required by the platform to > + * operate correctly. > + * Until the following condition are met, we need this clock to > + * be marked as critical: > + * a) Mark the clock used by a firmware resource, if possible > + * b) CCF has a clock hand-off mechanism to make the sure the > + * clock stays on until the proper driver comes along > + */ > + .flags = CLK_IS_CRITICAL, > }, > };
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index fad616cac01e..6d44cadc06af 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -298,6 +298,17 @@ static struct clk_regmap g12a_fclk_div2 = { &g12a_fclk_div2_div.hw }, .num_parents = 1, + /* + * Similar to fclk_div3, it seems that this clock is used by + * the resident firmware and is required by the platform to + * operate correctly. + * Until the following condition are met, we need this clock to + * be marked as critical: + * a) Mark the clock used by a firmware resource, if possible + * b) CCF has a clock hand-off mechanism to make the sure the + * clock stays on until the proper driver comes along + */ + .flags = CLK_IS_CRITICAL, }, };