diff mbox series

[4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC

Message ID 58225ced4893018792d581c0476a0f1c70e08907.1615221459.git.cristian.ciocaltea@gmail.com (mailing list archive)
State New, archived
Headers show
Series Improve clock support for Actions S500 SoC | expand

Commit Message

Cristian Ciocaltea March 8, 2021, 5:18 p.m. UTC 
There are a few issues with the setup of the Actions Semi Owl S500 SoC's
clock chain involving AHPPREDIV, H and AHB clocks:

* AHBPREDIV clock is defined as a muxer only, although it also acts as
  a divider.
* H clock is defined as a standard divider, although the raw value zero
  is not supported.
* AHB is defined as a multi-rate factor clock, but it is actually just
  a fixed pass clock.

Let's provide the following fixes:

* Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition.
* Add a clock div table 'h_div_table' for the H clock to drop the
  unsupported 0 rate and use the correct register shift value in the
  OWL_DIVIDER definition.
* Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an
  ungated OWL_COMP_FIXED_FACTOR definition.

Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 drivers/clk/actions/owl-s500.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

Comments

Manivannan Sadhasivam March 16, 2021, 5:45 a.m. UTC | #1 
On Mon, Mar 08, 2021 at 07:18:29PM +0200, Cristian Ciocaltea wrote:
> There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> clock chain involving AHPPREDIV, H and AHB clocks:
> 
> * AHBPREDIV clock is defined as a muxer only, although it also acts as
>   a divider.
> * H clock is defined as a standard divider, although the raw value zero
>   is not supported.

What do you mean by not supported? The datasheet lists "0" as the valid divisor
value for divide by 1.

Rest looks good to me.

Thanks,
Mani

> * AHB is defined as a multi-rate factor clock, but it is actually just
>   a fixed pass clock.
> 
> Let's provide the following fixes:
> 
> * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition.
> * Add a clock div table 'h_div_table' for the H clock to drop the
>   unsupported 0 rate and use the correct register shift value in the
>   OWL_DIVIDER definition.
> * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an
>   ungated OWL_COMP_FIXED_FACTOR definition.
> 
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
>  drivers/clk/actions/owl-s500.c | 20 ++++++++++++++------
>  1 file changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index abe8874353de..b9e434173b4f 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -151,9 +151,9 @@ static struct clk_factor_table hde_factor_table[] = {
>  	{ 0, 0, 0 },
>  };
>  
> -static struct clk_factor_table ahb_factor_table[] = {
> -	{ 1, 1, 2 }, { 2, 1, 3 },
> -	{ 0, 0, 0 },
> +static struct clk_div_table h_div_table[] = {
> +	{ 1, 2 }, { 2, 3 }, { 3, 4 },
> +	{ 0, 0 },
>  };
>  
>  static struct clk_div_table rmii_ref_div_table[] = {
> @@ -184,7 +184,6 @@ static struct clk_div_table nand_div_table[] = {
>  
>  /* mux clock */
>  static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
> -static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
>  
>  /* gate clocks */
>  static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
> @@ -197,16 +196,25 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
>  static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
>  
>  /* divider clocks */
> -static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, h_div_table, 0, 0);
>  static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
>  static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
>  
>  /* factor clocks */
> -static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
>  static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
>  static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
>  
>  /* composite clocks */
> +static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
> +			OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
> +			{ 0 },
> +			OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
> +			0);
> +
> +static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
> +			{ 0 },
> +			1, 1, CLK_SET_RATE_PARENT);
> +
>  static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
>  			OWL_MUX_HW(CMU_VCECLK, 4, 2),
>  			OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
> -- 
> 2.30.1
>
Cristian Ciocaltea March 16, 2021, 6:50 p.m. UTC | #2 
On Tue, Mar 16, 2021 at 11:15:47AM +0530, Manivannan Sadhasivam wrote:
> On Mon, Mar 08, 2021 at 07:18:29PM +0200, Cristian Ciocaltea wrote:
> > There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> > clock chain involving AHPPREDIV, H and AHB clocks:
> > 
> > * AHBPREDIV clock is defined as a muxer only, although it also acts as
> >   a divider.
> > * H clock is defined as a standard divider, although the raw value zero
> >   is not supported.
> 
> What do you mean by not supported? The datasheet lists "0" as the valid divisor
> value for divide by 1.

Unfortunately CMU_BUSCLK1 is not documented in my S500 Datasheet
(Version: 1.6, 2016-03-07). Do you have a newer (or a more official)
one?

The reference xapp-le code snipped is:

static struct owl_div divider_H_CLK = {
    .type = DIV_T_NATURE,
    .range_from = 1,  /* reserve H_CLK divsor 1 */
    .range_to = 3,
    .reg = &divbit_H_CLK,
};

Not sure why divisor 1 has been reserved..

Thanks,
Cristi

> Rest looks good to me.
> 
> Thanks,
> Mani
> 
[...]
Manivannan Sadhasivam May 26, 2021, 10:12 a.m. UTC | #3 
On Tue, Mar 16, 2021 at 08:50:14PM +0200, Cristian Ciocaltea wrote:
> On Tue, Mar 16, 2021 at 11:15:47AM +0530, Manivannan Sadhasivam wrote:
> > On Mon, Mar 08, 2021 at 07:18:29PM +0200, Cristian Ciocaltea wrote:
> > > There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> > > clock chain involving AHPPREDIV, H and AHB clocks:
> > > 
> > > * AHBPREDIV clock is defined as a muxer only, although it also acts as
> > >   a divider.
> > > * H clock is defined as a standard divider, although the raw value zero
> > >   is not supported.
> > 
> > What do you mean by not supported? The datasheet lists "0" as the valid divisor
> > value for divide by 1.
> 
> Unfortunately CMU_BUSCLK1 is not documented in my S500 Datasheet
> (Version: 1.6, 2016-03-07). Do you have a newer (or a more official)
> one?
> 

Yes I do have a newer version of the datasheet (v1.8) and there I can
see the divisor 0.

> The reference xapp-le code snipped is:
> 
> static struct owl_div divider_H_CLK = {
>     .type = DIV_T_NATURE,
>     .range_from = 1,  /* reserve H_CLK divsor 1 */
>     .range_to = 3,
>     .reg = &divbit_H_CLK,
> };
> 
> Not sure why divisor 1 has been reserved..
> 

It is not as per the datasheet. Did you run into any issues with this?
Else I'd suggest to keep it as it is.

Thanks,
Mani

> Thanks,
> Cristi
> 
> > Rest looks good to me.
> > 
> > Thanks,
> > Mani
> > 
> [...]
Cristian Ciocaltea May 27, 2021, 1:45 p.m. UTC | #4 
On Wed, May 26, 2021 at 03:42:30PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Mar 16, 2021 at 08:50:14PM +0200, Cristian Ciocaltea wrote:
> > On Tue, Mar 16, 2021 at 11:15:47AM +0530, Manivannan Sadhasivam wrote:
> > > On Mon, Mar 08, 2021 at 07:18:29PM +0200, Cristian Ciocaltea wrote:
> > > > There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> > > > clock chain involving AHPPREDIV, H and AHB clocks:
> > > > 
> > > > * AHBPREDIV clock is defined as a muxer only, although it also acts as
> > > >   a divider.
> > > > * H clock is defined as a standard divider, although the raw value zero
> > > >   is not supported.
> > > 
> > > What do you mean by not supported? The datasheet lists "0" as the valid divisor
> > > value for divide by 1.
> > 
> > Unfortunately CMU_BUSCLK1 is not documented in my S500 Datasheet
> > (Version: 1.6, 2016-03-07). Do you have a newer (or a more official)
> > one?
> > 
> 
> Yes I do have a newer version of the datasheet (v1.8) and there I can
> see the divisor 0.

I got an updated datasheet (v1.9) and I confirm dividing by 1 is valid.

> > The reference xapp-le code snipped is:
> > 
> > static struct owl_div divider_H_CLK = {
> >     .type = DIV_T_NATURE,
> >     .range_from = 1,  /* reserve H_CLK divsor 1 */
> >     .range_to = 3,
> >     .reg = &divbit_H_CLK,
> > };
> > 
> > Not sure why divisor 1 has been reserved..
> > 
> 
> It is not as per the datasheet. Did you run into any issues with this?
> Else I'd suggest to keep it as it is.

I reverted the changes (please see v2) and did not encounter any issues
so far, so let's ignore the vendor driver implementation.

Thanks for the review,
Cristi

> Thanks,
> Mani
> 
> > Thanks,
> > Cristi
> > 
> > > Rest looks good to me.
> > > 
> > > Thanks,
> > > Mani
> > > 
> > [...]
diff mbox series

Patch

diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index abe8874353de..b9e434173b4f 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -151,9 +151,9 @@  static struct clk_factor_table hde_factor_table[] = {
 	{ 0, 0, 0 },
 };
 
-static struct clk_factor_table ahb_factor_table[] = {
-	{ 1, 1, 2 }, { 2, 1, 3 },
-	{ 0, 0, 0 },
+static struct clk_div_table h_div_table[] = {
+	{ 1, 2 }, { 2, 3 }, { 3, 4 },
+	{ 0, 0 },
 };
 
 static struct clk_div_table rmii_ref_div_table[] = {
@@ -184,7 +184,6 @@  static struct clk_div_table nand_div_table[] = {
 
 /* mux clock */
 static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
-static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
 
 /* gate clocks */
 static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
@@ -197,16 +196,25 @@  static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
 static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
 
 /* divider clocks */
-static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, h_div_table, 0, 0);
 static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
 static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
 
 /* factor clocks */
-static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
 static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
 static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
 
 /* composite clocks */
+static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
+			OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
+			{ 0 },
+			OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
+			0);
+
+static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
+			{ 0 },
+			1, 1, CLK_SET_RATE_PARENT);
+
 static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
 			OWL_MUX_HW(CMU_VCECLK, 4, 2),
 			OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),