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Received: from [45.249.212.188] (helo=dggrg02-dlp.huawei.com) by casper.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cnj06-0002vs-3J for linux-arm-kernel@lists.infradead.org; Tue, 14 Mar 2017 09:44:21 +0000 Received: from 172.30.72.56 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.56]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AJY15126; Tue, 14 Mar 2017 17:35:36 +0800 (CST) Received: from [127.0.0.1] (10.177.19.210) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Tue, 14 Mar 2017 17:35:24 +0800 Subject: Re: [PATCH V12 09/10] trace, ras: add ARM processor error trace event To: Steven Rostedt , "Baicar, Tyler" References: <1488833103-21082-1-git-send-email-tbaicar@codeaurora.org> <1488833103-21082-10-git-send-email-tbaicar@codeaurora.org> <58C12342.2090701@huawei.com> <14545228-7ff1-b31c-1fa5-daacf89a44b9@codeaurora.org> <58C60485.2070509@huawei.com> <58C65FCB.3040508@huawei.com> <20170313095852.0c424d53@gandalf.local.home> From: Xie XiuQi Message-ID: <58C7B955.50909@huawei.com> Date: Tue, 14 Mar 2017 17:35:17 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:42.0) Gecko/20100101 Thunderbird/42.0a1 MIME-Version: 1.0 In-Reply-To: <20170313095852.0c424d53@gandalf.local.home> X-Originating-IP: [10.177.19.210] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.58C7B96D.008F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 81079134d73618e5e305ff9eb3a9c110 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170314_094419_334747_85D7CCDC X-CRM114-Status: GOOD ( 26.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-efi@vger.kernel.org, kvm@vger.kernel.org, rkrcmar@redhat.com, matt@codeblueprint.co.uk, catalin.marinas@arm.com, will.deacon@arm.com, robert.moore@intel.com, paul.gortmaker@windriver.com, lv.zheng@intel.com, Guo Hanjun , kvmarm@lists.cs.columbia.edu, fu.wei@linaro.org, tn@semihalf.com, zjzhang@codeaurora.org, linux@armlinux.org.uk, "wangxiongfeng2@huawei.com" , linux-acpi@vger.kernel.org, eun.taik.lee@samsung.com, shijie.huang@arm.com, labbott@redhat.com, lenb@kernel.org, harba@codeaurora.org, john.garry@huawei.com, Suzuki.Poulose@arm.com, marc.zyngier@arm.com, punit.agrawal@arm.com, nkaje@codeaurora.org, sandeepa.s.prabhu@gmail.com, "Zhengqiang \(turing\)" , linux-arm-kernel@lists.infradead.org, devel@acpica.org, rjw@rjwysocki.net, rruigrok@codeaurora.org, linux-kernel@vger.kernel.org, astone@redhat.com, james.morse@arm.com, hanjun.guo@linaro.org, joe@perches.com, pbonzini@redhat.com, akpm@linux-foundation.org, bristot@redhat.com, christoffer.dall@linaro.org, shiju.jose@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Steven, Thanks for you comments. As your suggestion, I've changed it in v2. From c29c14c3b960f55beb4c4b22b7aced64fa7daf9a Mon Sep 17 00:00:00 2001 From: Xie XiuQi Date: Mon, 13 Mar 2017 15:46:06 +0800 Subject: [PATCH v2] trace: ras: add ARM processor error information trace event Add a new trace event for ARM processor error information, so that the user will know what error occurred. With this information the user may take appropriate action. These trace events are consistent with the ARM processor error information table which defined in UEFI 2.6 spec section N.2.4.4.1. --- v2: add trace enabled condition as Steven's suggestion. fix a typo. Signed-off-by: Xie XiuQi --- drivers/acpi/apei/ghes.c | 10 ++++++ include/linux/cper.h | 5 +++ include/ras/ras_event.h | 87 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 251d7e0..bcb8160 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -518,9 +518,19 @@ static void ghes_do_proc(struct ghes *ghes, else if (!uuid_le_cmp(sec_type, CPER_SEC_PROC_ARM) && trace_arm_event_enabled()) { struct cper_sec_proc_arm *arm_err; + struct cper_arm_err_info *err_info; + int i; arm_err = acpi_hest_generic_data_payload(gdata); trace_arm_event(arm_err); + + if (trace_arm_proc_err_enabled()) { + err_info = (struct cper_arm_err_info *)(arm_err + 1); + for (i = 0; i < arm_err->err_info_num; i++) { + trace_arm_proc_err(err_info); + err_info += 1; + } + } } else if (trace_unknown_sec_event_enabled()) { void *unknown_err = acpi_hest_generic_data_payload(gdata); trace_unknown_sec_event(&sec_type, diff --git a/include/linux/cper.h b/include/linux/cper.h index 85450f3..0cae900 100644 --- a/include/linux/cper.h +++ b/include/linux/cper.h @@ -270,6 +270,11 @@ enum { #define CPER_ARM_INFO_VALID_VIRT_ADDR 0x0008 #define CPER_ARM_INFO_VALID_PHYSICAL_ADDR 0x0010 +#define CPER_ARM_INFO_TYPE_CACHE 0 +#define CPER_ARM_INFO_TYPE_TLB 1 +#define CPER_ARM_INFO_TYPE_BUS 2 +#define CPER_ARM_INFO_TYPE_UARCH 3 + #define CPER_ARM_INFO_FLAGS_FIRST 0x0001 #define CPER_ARM_INFO_FLAGS_LAST 0x0002 #define CPER_ARM_INFO_FLAGS_PROPAGATED 0x0004 diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index b36db48..0f9f46e 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -195,6 +195,93 @@ __entry->running_state, __entry->psci_state) ); +#define ARM_PROC_ERR_TYPE \ + EM ( CPER_ARM_INFO_TYPE_CACHE, "cache error" ) \ + EM ( CPER_ARM_INFO_TYPE_TLB, "TLB error" ) \ + EM ( CPER_ARM_INFO_TYPE_BUS, "bus error" ) \ + EMe ( CPER_ARM_INFO_TYPE_UARCH, "micro-architectural error" ) + +#define ARM_PROC_ERR_FLAGS \ + EM ( CPER_ARM_INFO_FLAGS_FIRST, "First error captured" ) \ + EM ( CPER_ARM_INFO_FLAGS_LAST, "Last error captured" ) \ + EM ( CPER_ARM_INFO_FLAGS_PROPAGATED, "Propagated" ) \ + EMe ( CPER_ARM_INFO_FLAGS_OVERFLOW, "Overflow" ) + +/* + * First define the enums in MM_ACTION_RESULT to be exported to userspace + * via TRACE_DEFINE_ENUM(). + */ +#undef EM +#undef EMe +#define EM(a, b) TRACE_DEFINE_ENUM(a); +#define EMe(a, b) TRACE_DEFINE_ENUM(a); + +ARM_PROC_ERR_TYPE +ARM_PROC_ERR_FLAGS + +/* + * Now redefine the EM() and EMe() macros to map the enums to the strings + * that will be printed in the output. + */ +#undef EM +#undef EMe +#define EM(a, b) { a, b }, +#define EMe(a, b) { a, b } + +TRACE_EVENT(arm_proc_err, + + TP_PROTO(const struct cper_arm_err_info *err), + + TP_ARGS(err), + + TP_STRUCT__entry( + __field(u8, type) + __field(u16, multiple_error) + __field(u8, flags) + __field(u64, error_info) + __field(u64, virt_fault_addr) + __field(u64, physical_fault_addr) + ), + + TP_fast_assign( + __entry->type = err->type; + + if (err->validation_bits & CPER_ARM_INFO_VALID_MULTI_ERR) + __entry->multiple_error = err->multiple_error; + else + __entry->multiple_error = ~0; + + if (err->validation_bits & CPER_ARM_INFO_VALID_FLAGS) + __entry->flags = err->flags; + else + __entry->flags = ~0; + + if (err->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO) + __entry->error_info = err->error_info; + else + __entry->error_info = 0ULL; + + if (err->validation_bits & CPER_ARM_INFO_VALID_VIRT_ADDR) + __entry->virt_fault_addr = err->virt_fault_addr; + else + __entry->virt_fault_addr = 0ULL; + + if (err->validation_bits & CPER_ARM_INFO_VALID_PHYSICAL_ADDR) + __entry->physical_fault_addr = err->physical_fault_addr; + else + __entry->physical_fault_addr = 0ULL; + ), + + TP_printk("ARM Processor Error: type %s; count: %u; flags: %s;" + " error info: %016llx; virtual address: %016llx;" + " physical address: %016llx", + __print_symbolic(__entry->type, ARCH_PROC_ERR_TYPE), + __entry->multiple_error, + __print_symbolic(__entry->flags, ARCH_PROC_ERR_FLAGS), + __entry->error_info, __entry->virt_fault_addr, + __entry->physical_fault_addr) +); + /* * Unknown Section Report *