From patchwork Wed Nov 4 23:18:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Konovalov X-Patchwork-Id: 11883193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 404C7C00A89 for ; Thu, 5 Nov 2020 04:41:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B342D2087D for ; Thu, 5 Nov 2020 04:41:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="yVxEG4cM"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="D9DBABAP"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=google.com header.i=@google.com header.b="QOLfmd7s" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B342D2087D Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:To:From:Subject:References:Mime-Version:Message-Id: In-Reply-To:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5w6AVDPWUxdinGOJnJIV30xs1ta4Kgn8vWmKOG8Y3hs=; b=yVxEG4cMR045PoaGKzu2g1+2d Jdj9H87uKpGA/BCyogTLWxE4th5UUxTMn+NzIu4WtnWH/VDpT+OhaJRuFx7udO3LQsXZ5tDEeDARr uKi68gQKv81hyTppGXNNxbH6BSuB7VgVgmkJI8pO9TEM5k2sndDI3lOyuIz9g1/Dy4+x4ECm+0kUQ lv9Y335EO+FR8lZ8e0WLWRJtJUD6C8fHZMHfXmuxCcIc8FVXGMYqyWA0FoUGm4lG4pjLjFXJXHVB0 Bsa8wrkQnGhCOjjapojYUm3cHzKw5M6IA3ElcqJ/tWZbYMDXF9WoisJEvq6t6yBRAQlftVOvFTjuX nvT+squ6g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaX4n-0005II-1R; Thu, 05 Nov 2020 04:40:45 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaW58-00016k-Gg for linux-arm-kernel@merlin.infradead.org; Thu, 05 Nov 2020 03:37:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Type:Cc:To:From:Subject: References:Mime-Version:Message-Id:In-Reply-To:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=1s7WiGrMcWP0bJ51auKgm3tMrSQZgmfW9W//QveyJyE=; b=D9DBABAPqXMJ1alrYuMzFGjQ1f mWzscZ48BKnotlWKH8SnAzabSsw8pzKVlAWRtsV60y98QDTUz8CqIY+d8i0Lw/zBebpSBjVDmqGHS piW6MHW0rtUS0dyyFvfBoXfIlpoJkw8rmVhi/aR9IaWuTEvXXQqeIqserD+OgzxudI3R8lkBiKhM5 3ovMmVrGoIEaHE+31CdhOthtX/utNyLSXN5ougl8XufnKAVh/1j3lYVw9hVyokQWGBUXVwvDJnDi2 +Ebh2iquXDux55zANS/41WiLUF4t+JzYg6FLpugtAqMQ8VEWybujZt0Zbl4nE6vxvrX83N9OlxLIw ZfG4m3Fg==; Received: from mail-qv1-xf49.google.com ([2607:f8b0:4864:20::f49]) by casper.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaS5m-000481-9x for linux-arm-kernel@lists.infradead.org; Wed, 04 Nov 2020 23:21:28 +0000 Received: by mail-qv1-xf49.google.com with SMTP id z9so13820638qvo.20 for ; Wed, 04 Nov 2020 15:21:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:date:in-reply-to:message-id:mime-version:references:subject :from:to:cc; bh=1s7WiGrMcWP0bJ51auKgm3tMrSQZgmfW9W//QveyJyE=; b=QOLfmd7sbB/uHcXb5wG4vTPM4uHt/1CVewmjlPNqFyzageoNXn4omZNoVnXK8mis6c hRoYAdMud4+BWku4nKx5xtmWuwtV9oLzmGnX2l78tQ3K1WgvBl8dv476ARKMLdVXz78k /gC9aFpeF9KDKEZf8SlvWuPQdu+jhJzPn9dTJiPml6gqrNzw2h9sST6qwYnv1aHmv005 A0mdoleOwTFSoWX/dm5Ge7tYuDIst+yu7t5a8P71me7pYKCkoggtYaYDhWMaDvyAGhUp MEDKzC9vmGMr9INVgMH7pGOxF8FY1/9KpxARjuLdbrlFVeGCOeXq4BthxOzrCg3w4gBs atVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=1s7WiGrMcWP0bJ51auKgm3tMrSQZgmfW9W//QveyJyE=; b=Po+NDVHHWeQXcxvA6ngVRBGTVpoi2kJNx/s3vD3eKD18hvPlI+Xlw2SfUn4NNcIRLC mVP3VxHZ5XVfdi7LjdzgtFwNX90CFxnFxLqztONmAdlO/+o5MavewDE9XhcDEDKHIhUz i0VP1nfulxyTvZZz/Y+KBaRFrqXkc1msRQqJ0aeA/7xUNoL0nGExrKWqj/OWyiLbLQYy YykXNRR61nwIAWENxF5XL0rqi+cKB/vmQtVsD8wE9LNBfP13whLUn49TufHwMnG9dMlM LLIBqvqrhlmzuhcHvk32E3ogiplOWl7il1cX76vKgoankCmhyDYHdOpA76zDehbZFWEe 5GPw== X-Gm-Message-State: AOAM5316OdVI1rQyDZuQ4meBbym7QjnDjM+oLlbJYo1CXXm2Vmj11fib BhuI1l56W8kVshLP/jU82GpPZk4XfuRV31rh X-Google-Smtp-Source: ABdhPJyN+NYstL7F4/h7rv7aydUP0ySpi6gyHswA7hqJRVdOqBM8y3b9JxfArhQ8KqMAFVmV39FMkmg/iNsjO9zi X-Received: from andreyknvl3.muc.corp.google.com ([2a00:79e0:15:13:7220:84ff:fe09:7e9d]) (user=andreyknvl job=sendgmr) by 2002:ad4:55ea:: with SMTP id bu10mr282677qvb.28.1604532023877; Wed, 04 Nov 2020 15:20:23 -0800 (PST) Date: Thu, 5 Nov 2020 00:18:47 +0100 In-Reply-To: Message-Id: <5d9ece04df8e9d60e347a2f6f96b8c52316bfe66.1604531793.git.andreyknvl@google.com> Mime-Version: 1.0 References: X-Mailer: git-send-email 2.29.1.341.ge80a0c044ae-goog Subject: [PATCH v8 32/43] arm64: mte: Switch GCR_EL1 in kernel entry and exit From: Andrey Konovalov To: Catalin Marinas X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201104_232126_505470_588B7EB5 X-CRM114-Status: GOOD ( 21.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Marco Elver , Andrey Konovalov , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev@googlegroups.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexander Potapenko , Evgenii Stepanov , Andrey Ryabinin , Andrew Morton , Vincenzo Frascino , Dmitry Vyukov Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Vincenzo Frascino When MTE is present, the GCR_EL1 register contains the tags mask that allows to exclude tags from the random generation via the IRG instruction. With the introduction of the new Tag-Based KASAN API that provides a mechanism to reserve tags for special reasons, the MTE implementation has to make sure that the GCR_EL1 setting for the kernel does not affect the userspace processes and viceversa. Save and restore the kernel/user mask in GCR_EL1 in kernel entry and exit. Signed-off-by: Vincenzo Frascino Co-developed-by: Andrey Konovalov Signed-off-by: Andrey Konovalov Reviewed-by: Catalin Marinas --- Change-Id: I0081cba5ace27a9111bebb239075c9a466af4c84 --- arch/arm64/include/asm/mte-def.h | 1 - arch/arm64/include/asm/mte.h | 2 ++ arch/arm64/kernel/asm-offsets.c | 3 +++ arch/arm64/kernel/entry.S | 41 ++++++++++++++++++++++++++++++++ arch/arm64/kernel/mte.c | 28 +++++++++++++++++++--- 5 files changed, 71 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/mte-def.h b/arch/arm64/include/asm/mte-def.h index 8401ac5840c7..2d73a1612f09 100644 --- a/arch/arm64/include/asm/mte-def.h +++ b/arch/arm64/include/asm/mte-def.h @@ -10,6 +10,5 @@ #define MTE_TAG_SHIFT 56 #define MTE_TAG_SIZE 4 #define MTE_TAG_MASK GENMASK((MTE_TAG_SHIFT + (MTE_TAG_SIZE - 1)), MTE_TAG_SHIFT) -#define MTE_TAG_MAX (MTE_TAG_MASK >> MTE_TAG_SHIFT) #endif /* __ASM_MTE_DEF_H */ diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h index cf1cd181dcb2..d02aff9f493d 100644 --- a/arch/arm64/include/asm/mte.h +++ b/arch/arm64/include/asm/mte.h @@ -18,6 +18,8 @@ #include +extern u64 gcr_kernel_excl; + void mte_clear_page_tags(void *addr); unsigned long mte_copy_tags_from_user(void *to, const void __user *from, unsigned long n); diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 7d32fc959b1a..dfe6ed8446ac 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -47,6 +47,9 @@ int main(void) #ifdef CONFIG_ARM64_PTR_AUTH DEFINE(THREAD_KEYS_USER, offsetof(struct task_struct, thread.keys_user)); DEFINE(THREAD_KEYS_KERNEL, offsetof(struct task_struct, thread.keys_kernel)); +#endif +#ifdef CONFIG_ARM64_MTE + DEFINE(THREAD_GCR_EL1_USER, offsetof(struct task_struct, thread.gcr_user_excl)); #endif BLANK(); DEFINE(S_X0, offsetof(struct pt_regs, regs[0])); diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index b295fb912b12..07646ef4f184 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -173,6 +173,43 @@ alternative_else_nop_endif #endif .endm + .macro mte_set_gcr, tmp, tmp2 +#ifdef CONFIG_ARM64_MTE + /* + * Calculate and set the exclude mask preserving + * the RRND (bit[16]) setting. + */ + mrs_s \tmp2, SYS_GCR_EL1 + bfi \tmp2, \tmp, #0, #16 + msr_s SYS_GCR_EL1, \tmp2 + isb +#endif + .endm + + .macro mte_set_kernel_gcr, tmp, tmp2 +#ifdef CONFIG_KASAN_HW_TAGS +alternative_if_not ARM64_MTE + b 1f +alternative_else_nop_endif + ldr_l \tmp, gcr_kernel_excl + + mte_set_gcr \tmp, \tmp2 +1: +#endif + .endm + + .macro mte_set_user_gcr, tsk, tmp, tmp2 +#ifdef CONFIG_ARM64_MTE +alternative_if_not ARM64_MTE + b 1f +alternative_else_nop_endif + ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER] + + mte_set_gcr \tmp, \tmp2 +1: +#endif + .endm + .macro kernel_entry, el, regsize = 64 .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 @@ -212,6 +249,8 @@ alternative_else_nop_endif ptrauth_keys_install_kernel tsk, x20, x22, x23 + mte_set_kernel_gcr x22, x23 + scs_load tsk, x20 .else add x21, sp, #S_FRAME_SIZE @@ -330,6 +369,8 @@ alternative_else_nop_endif /* No kernel C function calls after this as user keys are set. */ ptrauth_keys_install_user tsk, x0, x1, x2 + mte_set_user_gcr tsk, x0, x1 + apply_ssbd 0, x0, x1 .endif diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 14b0c19a33e3..cc7e0f8707f7 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -23,6 +23,8 @@ #include #include +u64 gcr_kernel_excl __ro_after_init; + static void mte_sync_page_tags(struct page *page, pte_t *ptep, bool check_swap) { pte_t old_pte = READ_ONCE(*ptep); @@ -123,6 +125,23 @@ void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag) void __init mte_init_tags(u64 max_tag) { + static bool gcr_kernel_excl_initialized = false; + + if (!gcr_kernel_excl_initialized) { + /* + * The format of the tags in KASAN is 0xFF and in MTE is 0xF. + * This conversion extracts an MTE tag from a KASAN tag. + */ + u64 incl = GENMASK(FIELD_GET(MTE_TAG_MASK >> MTE_TAG_SHIFT, + max_tag), 0); + + gcr_kernel_excl = ~incl & SYS_GCR_EL1_EXCL_MASK; + gcr_kernel_excl_initialized = true; + } + + /* Enable the kernel exclude mask for random tags generation. */ + write_sysreg_s(SYS_GCR_EL1_RRND | gcr_kernel_excl, SYS_GCR_EL1); + /* Enable MTE Sync Mode for EL1. */ sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_SYNC); isb(); @@ -163,7 +182,11 @@ static void update_gcr_el1_excl(u64 excl) static void set_gcr_el1_excl(u64 excl) { current->thread.gcr_user_excl = excl; - update_gcr_el1_excl(excl); + + /* + * SYS_GCR_EL1 will be set to current->thread.gcr_user_excl value + * by mte_set_user_gcr() in kernel_exit, + */ } void flush_mte_state(void) @@ -189,7 +212,6 @@ void mte_thread_switch(struct task_struct *next) /* avoid expensive SCTLR_EL1 accesses if no change */ if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); - update_gcr_el1_excl(next->thread.gcr_user_excl); } void mte_suspend_exit(void) @@ -197,7 +219,7 @@ void mte_suspend_exit(void) if (!system_supports_mte()) return; - update_gcr_el1_excl(current->thread.gcr_user_excl); + update_gcr_el1_excl(gcr_kernel_excl); } long set_mte_ctrl(struct task_struct *task, unsigned long arg)