Message ID | 6da7a035d56a943336f68dc0da77a47dba3dd69e.1665583435.git.geert+renesas@glider.be (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | arm64: dts: renesas: r8a779g0/white-hawk: Add RPC and QSPI FLASH support | expand |
On Wed, Oct 12, 2022 at 04:06:50PM +0200, Geert Uytterhoeven wrote: > From: Hai Pham <hai.pham.ud@renesas.com> > > Add a device node for the SPI Multi I/O Bus Controller (RPC-IF) on the > Renesas R-Car V4H (R8A779G0) SoC. > > Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 33d9df39a9cc7149..8141ffc38a08301d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -921,6 +921,22 @@ mmc0: mmc@ee140000 { status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a779g0-rpc-if", + "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;