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h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U5HquPP+e02dVOAMk7E3AUX6XcA/ii1Z/T8jnzUactc=; b=aUXDeAUUTG+MoFS5XwUIdqHeMEMB2G9TDGMc0RGWXYVmsypNh+NiSEgHMl9rWz3Nec E9ElhRMnUD3HbjDf64i8gB5LFEN0X6G5fDm/Pb43VPSPmo9O+Ftg3v+3WyGR7osLadQm 8MernUmChyoAdMAkG2nzMV/E3T75RrO1hHmZghS302tzdGRBVyI0AsWZ1IPqt9gFCwR+ KzhL/NByfoLH/WepUxm7nzt1pBrz+pwCMf3lPcL3DkPMTO+G4LKi0jNbbfW18AzWNcXp ntG94C5dAu111pBf5NMIedhTva7ORPWxHbR8a6Fofzw5ch9G4ZYz0kVET6m9BdLpmiY+ L3mQ== X-Gm-Message-State: AA+aEWZcyTNcre0tD+cuLUHGocKQ/visWDnsUaLQ+vKX7JgOBmcDjT0O L+n1eBo9E0u6n4qJRAVRzQY= X-Google-Smtp-Source: AFSGD/W/OtAlyih/WhVzqPZsGD0/tqpYGnfDg3dN01pYvr42r9D/KeQrrTkyu7C0bVilnx/3ntMFew== X-Received: by 2002:adf:93e6:: with SMTP id 93-v6mr32350754wrp.311.1543444463336; Wed, 28 Nov 2018 14:34:23 -0800 (PST) Received: from ThinkPad.home ([185.219.177.239]) by smtp.gmail.com with ESMTPSA id g198sm180244wmd.23.2018.11.28.14.34.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Nov 2018 14:34:22 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v5 07/17] irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s Date: Thu, 29 Nov 2018 01:33:17 +0300 Message-Id: <6dbf7832bf743a44648a7eb5e3bb923750956a36.1543443475.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181128_143436_865580_603CEF09 X-CRM114-Status: GOOD ( 16.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mesih Kilinc , Julian Calaby , Linus Walleij , Daniel Lezcano , Russell King , Marc Zyngier , Chen-Yu Tsai , Rob Herring , Maxime Ripard , Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for suniv Allwinner ARMv5 F1C100s SoC which has stripped version of interrupt controller that found in A10/A13. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun4i.c | 47 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 507f4e3..fb78d66 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -32,6 +32,8 @@ #define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x) #define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 #define SUN4I_IRQ_MASK_REG_OFFSET 0x50 +#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20 +#define SUNIV_IRQ_MASK_REG_OFFSET 0x30 struct sun4i_irq_chip_data { void __iomem *irq_base; @@ -105,15 +107,6 @@ static const struct irq_domain_ops sun4i_irq_ops = { static int __init sun4i_of_init(struct device_node *node, struct device_node *parent) { - irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); - if (!irq_ic_data) { - pr_err("kzalloc failed!\n"); - return -ENOMEM; - } - - irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; - irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; - irq_ic_data->irq_base = of_iomap(node, 0); if (!irq_ic_data->irq_base) panic("%pOF: unable to map IC registers\n", @@ -149,7 +142,41 @@ static int __init sun4i_of_init(struct device_node *node, return 0; } -IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init); + +static int __init sun4i_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + + return sun4i_of_init(node, parent); +} + +IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init); + +static int __init suniv_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; + + return sun4i_of_init(node, parent); +} + +IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic", + suniv_ic_of_init); static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) {