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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id y42sm1606697wry.97.2018.04.11.06.55.02 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 11 Apr 2018 06:55:02 -0700 (PDT) From: Michal Simek To: linux-kernel@vger.kernel.org, monstr@monstr.eu Subject: [PATCH] gpio: zynq: Setup chip->base based on alias ID Date: Wed, 11 Apr 2018 15:55:01 +0200 Message-Id: <6ee982f8eb6e07f9ecbb0cc5093152f4a16b9c31.1523454899.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.17.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180411_065515_606771_EB194CED X-CRM114-Status: GOOD ( 14.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Crosthwaite , Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring , Steffen Trumtrar , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In past Xilinx gpio-zynq driver was setting up gpio chip->base as 0 which was chagned to autodetection when driver was upstreamed. Older systems, which were using this old version, setup SW stack which expects zynq gpio base as 0 and right now there is no way how to set this up. The patch is adding an option to setup chip->base based on aliases which is something what some other drivers are doing too. It means when gpio0 alias is setup then chip->base is 0. When gpio alias is not setup gpiochip_find_base() set it up properly which is current behavior. Signed-off-by: Michal Simek --- drivers/gpio/gpio-zynq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index 23bb10576def..412cb5f31a9b 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -831,7 +831,7 @@ static int zynq_gpio_probe(struct platform_device *pdev) chip->free = zynq_gpio_free; chip->direction_input = zynq_gpio_dir_in; chip->direction_output = zynq_gpio_dir_out; - chip->base = -1; + chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); chip->ngpio = gpio->p_data->ngpio; /* Retrieve GPIO clock */